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XRT86VL32IB Datasheet(PDF) 23 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 23 Page - Exar Corporation |
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23 / 153 page  XRT86VL3X 16 REV. 1.2.2 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION 1.13 High-Speed Multiplexed Interface In addition to the non-multiplexed mode, the framer can interface through the backplane in a high-speed multiplexed application, either through a bit-muxed or byte-muxed (in HMVIP or H.100) manner. In this mode, the chip is divided into two multiplexed blocks, four channels per block. For T1, the high speed multiplexed modes are 12.352Mbps (bit-muxed, TxSYNC is “High” during the F-bit), 16.384Mbps (bit-muxed, TxSYNC is “High” during the F-bit), 16.384Mbps (HMVIP: byte-muxed, TxSYNC is “High” during the last 2-bits of the previous frame and the first 2-bits of the current frame), or 16.384Mbps (H.100: byte-muxed, TxSYNC is “High” during the last bit of the previous frame and the first bit in the current frame). For E1 mode, the only mode that is not supported is the 12.352Mbps. The only other difference is that the F-bit (for T1 mode) becomes the first bit of the E1 frame. Figure 20 is a simplified block diagram of transmit bit-muxed application. Figure 21 is a simplified block diagram of receive bit-muxed application. Although the data is only applied to channel 4 or channel 0, the TxSERCLK is necessary for all channels so that the transmit line rate is always equal to the T1/ E1 carrier rate. FIGURE 20. TRANSMIT HIGH-SPEED BIT MULTIPLEXED BLOCK DIAGRAM FIGURE 21. RECEIVE HIGH-SPEED BIT MULTIPLEXED BLOCK DIAGRAM TxSER4 TxMSYNC4 (16.384MHz) TxSERCLK4 (2.048MHz) TxSERCLK5 (2.048MHz) TxSERCLK6 (2.048MHz) TxSERCLK7 (2.048MHz) TTIP/TRing4 TTIP/TRing5 TTIP/TRing6 TTIP/TRing7 4b0 4b0 5b0 5b0 6b0 6b0 7b0 7b0 4b1 4b1 5b1 5b1 6b1 6b1 7b1 7b1 4b2 4b2 5b2 5b2 6b2 6b2 7b2 7b2 4b0 4b1 4b2 5b0 5b1 5b2 6b0 6b1 6b2 7b0 7b1 7b2 DMUX TxSYNC4 Bit Interleaved Multiplexed Mode RxSER4 RxSERCLK4 (16.384MHz) RxLineClk4 (2.048MHz) RxLineClk5 (2.048MHz) RxLineClk6 (2.048MHz) RxLineClk7 (2.048MHz) RTIP/RRing4 RTIP/RRing5 RTIP/RRing6 RTIP/RRing7 4b0 0 0 5b0 0 6b0 7b0 0 4b1 0 0 5b1 0 6b1 7b1 0 4b2 0 0 5b2 0 6b2 7b2 0 4b0 4b1 4b2 5b0 5b1 5b2 6b0 6b1 6b2 7b0 7b1 7b2 MUX RxSYNC4 Bit Interleaved Multiplexed Mode RZ Data |
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