XRT86VL32IB datasheet(53/153 Pages) EXAR

53 / 153 page

XRT86VL3X

REV. 1.2.2

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

The table below shows configuration of the Receive Sa Data Link Select bits of the Receive Signaling and Data

Link Select Register (RSDLSR).

For every received Sa bit that is determined to carry Data Link information, the Receive Overhead Output

Interface will supply a clock pulse, via the RxOHClk_n output pin, such that:

• The Receive Overhead Output interface should update the data on the RxOH_n line before the rising edge of

RxOHClk_n.

• The external Data Link equipment interfaced to the Receive Overhead Output Interface will sample and latch

the data on the RxOH_n line on the rising edge of RxOHClk_n.

Figure 45

below shows the timing diagram of the output signals associated with the E1 Receive Overhead

Output Interface module in E1 framing format mode.

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (ADDRESS = 0XN10CH)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Receive Sa8 Data

Link Select

R/W

0 - The received Sa8 Nation bit is not extracted to the data link interface.

1 - The received Sa8 Nation bit is extracted to the data link interface.

Receive Sa7 Data

Link Select

R/W

0 - The received Sa7 Nation bit is not extracted to the data link interface.

1 - The received Sa7 Nation bit is extracted to the data link interface.

Receive Sa6 Data

Link Select

R/W

0 - The received Sa6 Nation bit is not extracted to the data link interface.

1 - The received Sa6 Nation bit is extracted to the data link interface.

Receive Sa5 Data

Link Select

R/W

0 - The received Sa5 Nation bit is not extracted to the data link interface.

1 - The received Sa5 Nation bit is extracted to the data link interface.

Receive Sa4 Data

Link Select

R/W

0 - The received Sa4 Nation bit is not extracted to the data link interface.

1 - The received Sa4 Nation bit is extracted to the data link interface.

FIGURE 45. E1 RECEIVE OVERHEAD OUTPUT INTERFACE TIMING

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