XRT86VL32IB datasheet(99/153 Pages) EXAR

99 / 153 page

XRT86VL3X

REV. 1.2.2

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable

When these interrupt enable bits are set and Red Alarm is present in the incoming DS1 frame, the XRT86VL3x

framer will declare Red Alarm by doing the following:

• Set the read-only Receive Red Alarm State bit of the Alarm and Error Status Register (AESR) to one

indicating there is Red Alarm detected in the incoming DS1 frame.

• Set the Receive Red Alarm State Change bit of the Alarm and Error Status Register to one indicating there is

a change in state of Red Alarm. This status indicator is valid until the Framer Interrupt Status Register is

read.

Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control

indicators.

The table below shows the Receive Red Alarm State Change status bits of the Alarm and Error Status

The Receive Red Alarm State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-

only bit indicating there is Red Alarm detected in the incoming DS1 frame.

The table below shows the Receive Red Alarm State status bits of the Alarm and Error Status Register.

9.3

Yellow Alarm

The Alarm indication logic within the Receive Framer block of the XRT86VL3x framer monitors the incoming

DS1 frames for Yellow Alarm condition. The yellow alarm is detected and declared according to the following

procedure:

BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0XNB01H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Alarm and Error

Interrupt Enable

R/W

0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-

ister (AEISR) is disabled.

1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-

ister (AEISR) is enabled.

ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0XNB02H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Receive Red Alarm

State Change

RUR /

0 - There is no change of Red Alarm state in the incoming DS1 payload

data.

1 - There is change of Red Alarm state in the incoming DS1 payload data.

ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0XNB02H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Receive Red Alarm

State

0 - There is no Red Alarm condition detected in the incoming DS1 payload

data.

1 - There is Red Alarm condition detected in the incoming DS1 payload

data.

XRT86VL32IB Datasheet(PDF) 99 Page - Exar Corporation

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