SC4000 datasheet(18/52 Pages) PHILIPS

18 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

Table 2. Conﬁguration Register Setup for SCbus Clock Master

Operation Mode

Conguration Register Bits Setup

Function Description

SCbus Master

C_0 = 1

SCbus clock master enabled

C_1 = 0

SCbus clock master disarmed (Default)

C_2

SCbus Primary or Alternate Select

0: Primary SCbus signals selected (Default)

1: Alternate SCbus signals selected

C_3 = 0

Diagnostic mode disabled

C_[5:4]

SCbus Framing mode to select one of the following rate:

0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)

10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame

11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame

C_[7:6]

Local bus Framing mode to select one of the following rate:

0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)

10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame

11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame

C_[10:8]

Master clock input frequency select:

000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz,

011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz,

11X =Reserved

C_21 = 0

SCbus FSYNCN rate to select one SCLK period (Default)

C_22

SCbus SCLKX2N and SCLKX2NA output enable control

0: SCbus SCLKX2N and SCLKX2NA output enabled (Default)

1: SCbus SCLKX2N and SCLKX2NA output disabled

C_23

SCbus Alternate signals output enable control

0: SCbus Alternate signals output disabled (Default)

1: SCbus Alternate signals output enabled

C_[43:40] (Internal/External

Master PLL reference 8K select)

Internal/External Master PLL reference select:

If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default),

001/010 = Free-run,

011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1,

110 = REF_8K_2, 111 = REF_8K_3

(see Figure 2)

If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from

C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 =

SREF_8K/SREF_8KA,

100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z)

(see Figure 3)

C_51 = 1

SCbus CLKFAIL latch debounce enabled

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