SC4000 datasheet(23/52 Pages) PHILIPS

23 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

MICROPROCESSOR INTERFACE

I/O Address Map

With Direct R/W to Parallel Access

Registers Disabled (C_11=0) (default)

With direct R/W to Parallel Access

Command / Status Register (Address = 0h)

Note:Setting more than one command

(Read, Write, Terminate or Reset) dur-

ing an access to the Command/Status

Busy (D_0) (Read Only)

This bit is set (“1”) when a command

that requires synchronization with the

SC4000’s internal state machine has

been initiated. This bit clears (“0”)

when the command is completed.

The following commands require

synchronization:

• Destination Routing Memory

Write command

• Source Routing Memory Write

command

• Indirect Parallel Access Destination

Write command

• Indirect Parallel Access Source

Read command

Read (D_1) (Write only)

Setting this bit (“1”) initiates a read of

the register pointed to by the Internal

Address Register. When the Busy bit is

clear (“0”), the contents of the register

to be read are available by reading the

Low byte & HighByte Data register. It is

not necessary to clear (“0”) this bit after

it has been set (“1”).

Note: Set this bit for an Indirect Parallel

Access Source Read (this is the only

“READ” requiring synchronization).

For reads which do not require synchro-

nization, the data registers can be read

immediately after writing the internal

address register.

Write (D_2) (Write only)

Setting this bit (“1”) initiates a write

to the register selected by the Internal

Address Register. When the Busy bit is

clear (“0”), the contents of the target

data stored in the Low Byte & High Byte

Data Register. It is not necessary to clear

(“0”) this bit after it has been set (“1”).

Terminate (D_3) (Read/Write)

Setting this bit (“1”) terminates a com-

mand that requires synchronization

with the SC4000’s internal state ma-

chine. This is necessary to complete a

command when the SC4000’s internal

state machine has stopped running (no

SCLK). The command in process is

completed asynchronously and the

Busy bit is cleared. It is necessary to clear

(“0”) this bit after it has been set (“1”).

Note : A new command (Read or Write)

should not be issued until after the

Terminate bit is cleared (“0”).

Channel Bank Select Register

[1:0] (D_[5:4]) (Read/Write)

This field determines the bank of chan-

nels that a command will affect. The

Channel Bank Select Register field is

combined with the Internal

Address Register to provide access to the

channel specific registers (routing and

parallel access). D_[5:4]) selects the

bank of channels to be accessed. This

field is cleared (“00”) on reset.

D_[5:4] = 00 -> Ch. 0 - 31

D_[5:4] = 01 -> Ch.32 - 63

D_[5:4] = 10 -> Ch.64 - 95

D_[5:4] = 11 -> Ch.96 - 127

Channel Bank Select Register Enable

(D_6) (Write only)

Writing to the command register with

this bit set (“1”) enables the Channel

bank select field to be changed. Writing

to the command register with this bit

cleared (“0”) causes the Channel Bank

Select Register field to retain its previous

value.

Note 1:The Channel Bank Select Regis-

ter may be changed during a write cycle

which also initiates a Read or Write

command. The Read or Write com-

mand affects the register pointed to by

the new value written into the Channel

Bank Select Register.

Note 2:The Channel Bank Select Regis-

ter should not be changed if the micro-

processor interface is busy.

Note 3:The Channel Bank Select Regis-

ter should not be changed during a write

cycle that either sets (0->1) or clears

(1->0) the Terminate command.

A_[1:0]

High Byte Data Register (HBDR)

Low Byte Data Register (LBDR)

Internal Address Register (IAR)

Command / Status Register

A_[8:0]

1FFh:180h

Source Parallel Access Register

Ch. 127:0

17Fh:100h

Destination Parallel Access Register

Ch. 127:0

0FFh:004h

Reserved

003h

High Byte Data Register (HBDR)

002h

Low Byte Data Register (LBDR)

001h

Internal Address Register (IAR)

000h

Command / Status Register

D_[7:0]

Definition

Busy (Read only)

Read Command (Write only)

Write Command (Write only)

Terminate Command (Read/Write)

[5:4]

Channel Bank Select Register [1:0]

(Read/Write)

Channel Bank Select Register Enable

(Write only)

Reset (Read/Write)

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