SC4000 datasheet(22/52 Pages) PHILIPS

22 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

The SC4000 features two address access

schemes. One is an indirect access

scheme (C_11 = 0) to reduce the num-

ber of pins required for the micropro-

cessor address bus interface from nine to

two (A_[1:0]), as shown in Figure 5. The

other is a combination of both indirect

and direct parallel access schemes (C_11

= 1). Using the combination requires

that all nine microprocessor address

pins (A_[8:0]) be used, as shown in

Figure 6.

Figure 5. Using Two Pins A_[1:0] for Address Bus Interface Scheme (C_11 = 0)

Figure 6. Using Nine Pins A_[8:0] for Address Bus Interface Scheme (C_11 = 1)

Microprocessor

Address

Data

03h

High Byte Data Register (HBDR)

02h

Low Byte Data Register (LBDR)

01h

Internal Address Register (IAR)

00h

Command/Status Register (CSR)

FFh - E0h

Source Parallel Access (31 - 0)

DFh - C0h

Destination Parallel Access (31 - 0)

BFh - A0h

Source Routing Memory (31 - 0)

9Fh - 80h

Destination Routing Memory (31 - 0)

7Fh - 0Dh

Reserved

0Ch - 00h

Configuration Register (12 - 0)

Note:See bit 5 and 4 of CSR to select

the bank of channels

A_[1:0]

D_[7:0]

FF - E0

Source Parallel Access (31 - 0)

DF - C0

Destination Parallel Access (31 - 0)

BF - A0

Source Routing Memory (31 - 0)

9F - 80

Destination Routing Memory (31 - 0)

7F - 0D

Reserved

0C - 00

Configuration Register (12 - 0)

Address

Data

1FFh - 180h

Source Parallel Access (127 - 0)

17Fh - 100h

Destination Parallel Access (127 - 0)

FFh - 04h

Reserved

03h

High Byte Data Register (HBDR)

02h

Low Byte Data Register (LBDR)

01h

Internal Address Register (IAR)

00h

Command/Status Register (CSR)

Note:See bit 5 and 4 of CSR to select

the bank of channels

Microprocessor

A_[8:0]

D_[7:0]

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