SC4000 datasheet(35/52 Pages) PHILIPS

35 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

4. Read Command/Status register and

test for NOT BUSY. (Note2)

5. Read contents of Low Byte Data regis-

ter and High Byte Data register as

required.

Note 1:It is not necessary to test for

NOT BUSY in this step if the protocol

used to access the SC4000 does not allow

the previous command to be completed

until the Command/Status register indi-

cates NOT BUSY.

Note 2:It is not necessary to test for

NOT BUSY in this step if the Command

given does not require synchronization

or if the protocol used to access the

SC4000 allows a command to be com-

pleted while the Command/Status regis-

ter indicates BUSY.

Note 3:It is not necessary to execute this

step if the Command given does not re-

quire synchronization.

Note 4:The Channel Bank Select field

may be changed during the same write

cycle which issues a command. The

command will effect the register pointed

to by the new value in the Channel Bank

Select Field.

Test

The Nand gate test chain is enabled by

forcing the TEST pin “high”. When in

test mode each pin is “nanded” with the

preceding pin and output at the end of

chain.

X_IN

D_0

REF_8K_0

D_1

REF_8K_1

D_2

REF_8K_2

D_3

REF_8K_3

D_4

TXD_0

D_5

RXD

D_6

MC_CLK

D_7

I_N

SCLKX2N

INT_0

SCLKX2NA

INT_1

SCLK

CS_0_N

SCLKA

CS_1_N

SREF_8K

RD_N

SREF_8KA

WR_N

FSYNCN

DACK_N

FSYNCNA

ALE

CLKFAIL

A_0

CLKFAILA

A_1

SD_0

A_2

SD_1

A_3

SD_2

A_4

SD_3

A_5

SD_4

A_6

SD_5

A_7

SD_6

A_8

SD_7

↓

SD_8

DRQ_R

SD_9

SD_10

SD_11

SD_12

SD_13

SD_14

SD_15

MCA

L_CLK

L_FS

SO_0

SO_1

SO_2

SO_3

SI_0

SI_1

SI_2

SI_3

RESET

↓

DRQ_T

SC4000 Datasheet(PDF) 35 Page - NXP Semiconductors

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