SC4000 datasheet(32/52 Pages) PHILIPS

32 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

SCbus SCLKX2NA Error Latch (C_65)

(Read only)

The SCbus SCLKX2NA Error Latch is

set when SCLKX2NA does not transi-

tion during the equivalent Master PLL

clock period.

0 -> SCbus SCLKX2NA Error Latch

Clear

1 -> SCbus SCLKX2NA Error Latch Set

SCbus SCLK Error Latch (C_66) (Read only)

The SCbus SCLK Error Latch is set when

SCLK does not transition during the

equivalent Master PLL clock period.

0 -> SCbus SCLK Error Latch Clear

1 -> SCbus SCLK Error Latch Set

SCbus SCLKA Error Latch (C_67) (Read only)

The SCbus SCLKA Error Latch is set

when SCLKA does not transition during

the equivalent Master PLL clock period.

0 -> SCbus SCLKA Error Latch Clear

1 -> SCbus SCLKA Error Latch Set

SCbus SCLKX2N Error Latch Clear_N (C_68)

(Read/Write)

0 ->SCbus SCLKX2N Error Latch held

clear (Default)

1 ->SCbus SCLKX2N Error Latch

enabled

SCbus SCLKX2NA Error Latch Clear_N

(C_69) (Read/Write)

0 ->SCbus SCLKX2NA Error Latch held

clear (Default)

1 ->SCbus SCLKX2NA Error Latch

enabled

SCbus SCLK Error Latch Clear_N (C_70)

(Read/Write)

0 ->SCbus SCLK Error Latch held clear

(Default)

1 ->SCbus SCLK Error Latch enabled

SCbus SCLKA Error Latch Clear_N(C_71)

(Read/Write)

0 ->SCbus SCLKA Error Latch held

clear (Default)

1 ->SCbus SCLKA Error Latch enabled

Configuration Register Byte 9, IAR = 09H

SCbus FSYNCN Error Latch (C_72)

(Read Only)

The SCbus FSYNCN Error Latch is set

when FSYNCN does not transition

during the equivalent Master PLL clock

period.

0 ->SCbus FSYNCN Error Latch Clear

1 ->SCbus FSYNCN Error Latch Set

SCbus FSYNCNA Error Latch (C_73)

(Read Only)

The SCbus FSYNCNA Error Latch is set

when FSYNCNA does not transition

during the equivalent Master PLL clock

period.

0 ->SCbus FSYNCNA Error Latch Clear

1 ->SCbus FSYNCNA Error Latch Set

SCbus Clock Master Error Latch (C_74)

(Read Only)

The SCbus Clock Master Error Latch is

set when the SC4000 is configured to be

Clock Master and the internally gener-

ated frame sync signal and SCbus

FSYNCN are not equal. This feature is

provided to detect when more than one

SCbus device is enabled as Clock Master

(i.e. two device driving FSYNCN).

0 ->SCbus Clock Master Error Latch

Clear

1 ->SCbus Clock Master Error Latch Set

SCbus FSYNCN Error Latch Clear_N (C_76)

(Read/Write)

0 ->SCbus FSYNCN Error Latch held

clear (Default)

1 ->SCbus FSYNCN Error Latch

enabled

SCbus FSYNCNA Error Latch Clear_N (C_77)

(Read/Write)

0 ->SCbus FSYNCNA Error Latch held

clear

1 ->SCbus FSYNCNA Error Latch

enabled

SCbus Clock Master Error Latch Clear_N

(C_78) (Read/Write)

0 ->SCbus Clock Master Error Latch

held clear (Default)

1 ->SCbus Clock Master Error Latch

enabled

Configuration Register Byte 10, IAR = 0AH

NE: Not Equal

LBDR_[7:0]

C_[79:72]

Definition

SCbus FSYNCN

Error Latch

(Read Only)

SCbus FSYNCNA

Error Latch

(Read Only)

SCbus Clock Mas-

ter Error Latch (Read

Only)

Reserved (0)

(Read Only)

SCbus FSYNCN

Error Latch Clear_n

SCbus FSYNCNA

Error Latch Clear_n

SCbus Clock

Master Error Latch

Clear_n

Reserved (0)

(Read Only)

LBDR_[7:0]

C_[87:80]

Definition

SCbus SREF_8K NE

SREF_8KA Error

Latch (Read only)

SCbus CLKFAIL NE

CLKFAILA Error

Latch (Read only)

SCbus MC NE MCA

Error Latch

(Read only)

SCbus SD Error Indi-

cator (Read only)

SCbus SREF_8K NE

SREF_8KA Error

Latch Clear_n

SCbus CLKFAIL NE

CLKFAILA Error

Latch Clear_n

SCbus MC NE MCA

Error Latch Clear_n

SCbus SD Error Latch

Clear_n

SC4000 Datasheet(PDF) 32 Page - NXP Semiconductors

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