AD7293 datasheet(31/79 Pages) AD

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Data Sheet

AD7293

Rev. D | Page 31 of 79

GPIO0 to GPIO3 Routing to ALERT1

A bit in the general register allows the GPIO0 to GPIO3 status

to route to the ALERT1 pin. Set GPIO0 to GPIO3 up as inputs

(bit set to 0 in the digital output enable register). If the GPIO is

read as 1, this read appears on ALERT1, and the GPIO register

can be read for the status of the pin to detect which pin has

caused ALERT1 to become active.

AVDD AND AVSS ALARM

There are comparators on AVDD (+3.6 V typical) and AVSS

(−4.1 V typical) that can be routed to the ALERTx pins or can

be used to control the PA_ON state and to put the bipolar

DACs/integrator outputs in the clamp state. By default, these

alarms are enabled.

When AVSS is greater than −4.1 V, there is a mask register

available whereby an alert of AVSS or AVDD is not creating an

alert on the ALERTx pin.

MAXIMUM AND MINIMUM PAGES

The maximum and minimum pages contain storage registers

for the maximum and minimum conversion results. This

function is useful when monitoring the minimum and maxi-

mum conversion values over time is required.

HYSTERESIS

The hysteresis value determines the reset point for the ALERTx

pin and/or software alert bit if a violation of the limits occurs. The

hysteresis register stores the hysteresis value when using the

limit registers. Each pair of limit registers has a dedicated hysteresis

device to detect an alert, the hysteresis can be useful to ensure

that no out of limit condition is missed.

HIGH LIMIT

LOW LIMIT

HIGH LIMIT – HYSTERESIS

LOW LIMIT + HYSTERESIS

TIME

INPUT SIGNAL

ALERT SIGNAL

Figure 50. Hysteresis

AD7293 Datasheet(PDF) 31 Page - Analog Devices