AD7293 datasheet(38/79 Pages) AD

38 / 79 page

AD7293

Data Sheet

Rev. D | Page 38 of 79

Conversion Delay Register (Register 0x1A)

This register can add a conversion delay (during the acquisition

phase) to the VINx channels in command mode conversions.

The resolution of this register is 320 ns. That is, each bit adds

320 ns to the conversion delay.

Temperature Sensor (TSENSEx) Background Enable

To enable the temperature sensor conversions, write to the

corresponding bit from this register. To enable digital filtering,

also write to the corresponding bit.

Current Sensor (ISENSEx) Background Enable Register

(Register 0x1C)

To enable the ISENSEx conversions, write to the corresponding bit

from this register. To enable digital filtering, also write to the

corresponding bit.

Current Sensor (ISENSEx) Gain Register (Register 0x1D)

The ISENSEx gain register is a 16-bit register that controls the gain

settings for the four current sense channels.

DAC Snooze/SLEEP0 Pin Register (Register 0x1F)

To clamp the relevant DAC output via the GPIO5/SLEEP0 pin

set the corresponding bit in this register to 1. The snooze bits

determine the power-up/power-down condition of the DACs

after removing the clamp signal. If any of the snooze bits are set

to 1, an additional write to the DAC enable register is required

to wake up the corresponding DAC. If the snooze bits are not

set, directly use the SLEEP0 pin to wake up the DAC.

DAC Snooze/SLEEP1 Pin Register (Register 0x20)

To clamp the relevant DAC output via the GPIO6/SLEEP1 pin,

set the corresponding bit in this register to 1.

RSx+MON, Supply Monitor, BI-VOUTx Background Enable

The RSx+MON and voltage supply channels can convert in the

background by setting the corresponding enable bit to 1.

Integrator Limit and Closed-Loop Control Register

(Register 0x28)

This register configures the device in closed-loop mode and

controls the integrator limit function as described in the

Closed-Loop Integrator Programmable Voltage Limit section.

PA_ON Control Register (Register 0x29)

This register controls the PA_ON pin and allows AVss/AVDD

alarm control over the PA_ON pin. Note that the AVSS/AVDD

alarm must be cleared before the PA_ON pin can switch back to

the on state.

This register also allows clamp pin control over the PA_ON pin.

Setting the clamp bit to 1 allows control of the PA_ON pin via

the SLEEP0 and SLEEP1 pins, where, if the pin goes high, the

PA_ON pin goes to the off state. If the snooze bit is set to 1, an

additional write to this register is required to set the PA_ON pin

to the on state after clearing the corresponding SLEEP0 and

SLEEP1 pins.

Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to

These 16-bit registers (Ramp Time 0 to Ramp Time 3) configure

the ramp time for the closed-loop channels. The resolution of

each bit is 250 µs and the maximum programmable ramp time

is 31.75 ms.

The minimum programmable ramp time for each channel is

4 ms. Enter 0x0000 to disable the ramp circuitry and to have the

DAC resolve the target value immediately.

Closed-Loop Fast Ramp and Integrator Time Constant

Use this register to disable or to enable the fast ramp scheme for

the closed-loop channels when they release from clamp. The

integrator time constant can trim to the values shown in Table 50.

Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD

Alarm Mask Register (Register 0x2F)

Use this 16-bit register to mask any of the closed-loop integrator

limit active status values or the AVss/AVDD alarm. When masked,

the status values are not visible when reading back the correspond-

ing alert registers, or if the status values are routed to any of the

ALERTx pins.

Table 32. Digital Output Enable Register (Register 0x11)

Bit Number(s)

Bit Name

Description

[D15:D8]

Reserved

GPIO7/LDAC (Pin 6)