AD7293 datasheet(37/79 Pages) AD

37 / 79 page

Data Sheet

AD7293

Rev. D | Page 37 of 79

CONFIGURATION (PAGE 0x02)

This page contains the registers that configure the device

operation.

Table 31. Configuration (Page 0x2)

Address

(Hex)

Name

Byte1

Access

Type1

Default

Value1

0x00

No op

N/A

0x00

0x01

Page select pointer

R/W

0x00

0x02

Conversion command2

N/A

0x03

Result

0x0000

0x04

DAC enable

R/W

0x00

0x05

GPIO

R/W

0x00

0x0C

Device ID

0x0018

0x0F

Software reset

R/W

0x0000

0x11

Digital output enable

R/W

0x0010

0x12

Digital input/output

function

R/W

0x000F

0x13

Digital functional

polarity

R/W

0x0090

0x14

General

R/W

0x0000

0x15

VINx Range 0

R/W

0x0000

0x16

VINx Range 1

R/W

0x0000

0x17

VINx differential/

single-ended enable

R/W

0x0000

0x18

VINx filter

R/W

0x0000

0x19

VINx background enable

R/W

0x0000

0x1A

Conversion delay

R/W

0x0000

0x1B

TSENSEx background

enable

R/W

0x0000

0x1C

ISENSEx background

enable

R/W

0x0000

0x1D

ISENSEx gain

R/W

0x0000

0x1F

DAC snooze/SLEEP0

R/W

0xFF00

0x20

DAC snooze/SLEEP1

R/W

0xFF00

0x23

RSx+MON, supply

monitor, BI-VOUTx

background enable

R/W

0x0000

0x28

Integrator limit and

closed-loop control

R/W

0x0000

0x29

PA_ON control

R/W

0x0130

0x2A

Ramp Time 0

R/W

0x0000

0x2B

Ramp Time 1

R/W

0x0000

0x2C

Ramp Time 2

R/W

0x0000

0x2D

Ramp Time 3

R/W

0x0000

0x2E

Closed-loop fast ramp

and integrator time

constant

R/W

0xBBBB

0x2F

INTLIMITx and AVSS/

AVDD alarm mask

R/W

0x0000

N/A means not applicable.

Not a physical register.

Digital Output Enable Register (Register 0x11)

This 16-bit register enables the output drivers of the GPIO pins

by setting the corresponding bit to one. When using one of the

pins as an output in GPIO mode or functional mode (for alerts

or busy), the corresponding bit must be set.

Digital Input/Output Function Register (Register 0x12)

All GPIOs are in either functional mode (power-up) or GPIO

mode. The relevant GPIO pin is in GPIO mode when the

corresponding bit in this register is set to 1. The relevant GPIO

pin is in functional mode when the corresponding bit in this

four pins are in GPIO mode after a power-on reset.

Digital Functional Polarity Register (Register 0x13)

This register sets the polarity of the digital input/output pins in

functional mode only. The associated input/output signal can be

made active low by setting the corresponding bit in this register

to 1. Functional mode is set up in the digital input/output

function register (Register 0x12).

General Register (Register 0x14)

This 16-bit register selects the internal ADC reference or an

external reference and other general functions. The status on

GPIO0 to GPIO3 can be routed to ALERT1. Error amplifier

control over the integrator limit feature is also configurable in

this register. ALERT0 can be routed internally to clamp the

bipolar DACs.

VINx Range x Registers (Register 0x15 and Register 0x16)

These two 16-bit registers combine together to specify the input

range of the VINx channels. The default range is 4 × REFADC. If

either of the corresponding range bits from the two range

registers is set to one, the analog input voltage range is set to

2 × REFADC. If both the bits are set to one, the analog input

voltage range is REFADC. See Table 36 and Table 37 for range

selection. REFADC = 1.25 V.

VINx Differential/Single-Ended Enable Register

(Register 0x17)

This register runs the ADC conversions for the voltage input

channels in differential and pseudo differential mode. The

corresponding differential pairs for the channels are as follows:

VIN0 to VIN1 for Channel 0, VIN1 to VIN0 for Channel 1, VIN2 to

VIN3 for Channel 2, and VIN3 to VIN2 for Channel 3. The

differential mode bits are ignored when the device is in pseudo

differential mode.

VINx Filter Register (Register 0x18)

A digital filter can be applied to the conversion result of all four

VINx channels. Set the corresponding filter bit to 1 to apply the

digital filter.

VINx Background Enable Register (Register 0x19)

Set the corresponding enable bit to 1 to convert the VINx channels

in the background.

AD7293 Datasheet(PDF) 37 Page - Analog Devices

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