AD7293 datasheet(26/79 Pages) AD

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AD7293

Data Sheet

Rev. D | Page 26 of 79

OFFSET

REFIN

OUT

























where:

VREFIN = 2.5 V.

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 4095 for the 12-bit AD7293).

n is the resolution of the DAC.

VOFFSET = 0 V (0 V to +5 V range), −4 V (−4 V to +1 V range), or

−5 V (−5 V to 0 V range).

Table 16. Bipolar DAC Voltage Offset Ranges

Range (V)

0x000

0xFFF

VOFFSET (V )

0 to +5

0 V

2 V × VREFIN

−4 to +1

−1.6 V × VREFIN

0.4 V × VREFIN

−4

−5 to 0

−2 V × VREFIN

0 V

−5

The ADC can also monitor these four outputs.

The bipolar DACs in addition to the four current sensors in the

PA controller can operate as four independent closed-loop

drain current controllers (see the Closed-Loop Mode section).

RESISTOR

STRING

REF(+)

REF(–)

–3

2.5V

REF

INPUT

DAC

VCLAMPX

CLAMP/

DAC

ENABLE

RANGE

SELECT

BI-VOUTX

0V TO +5V

–4V TO +1V

–5V TO 0V

Figure 43. Bipolar DAC Architecture Block Diagram

Unipolar DACs

The unipolar DAC outputs, UNI-VOUT0, UNI-VOUT1, UNI-

VOUT2, and UNI-VOUT3, can be configured through the offset

range registers to 0 to 5 V, 2.5 V to 7.5 V, or 5 V to 10 V (see

Table 84).

The DACs have one control register to control the interaction

between two registers: input registers and output registers. The

output registers contain the digital code used by the resistor

strings as well as a copy and load bit. Writing to these register

addresses sets the 12-bit DAC output voltage codes.

If the load bit is set to one, the device waits for LDAC to become

active before loading the voltage codes onto the DACs rather than

immediately after the write operation. If the copy bit is set to 1,

writing to a unipolar DAC registers sets all the other unipolar

DAC registers to the same value.

OFFSET

REFIN

OUT

























where:

VREFIN = 2.5 V.

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 4095 for the 12-bit AD7293).

n is the resolution of the DAC.

VOFFSET = 0 V (0 V to 5 V range), 2.5 V (2.5 V to 7.5 V range), or

5 V (5 V to 10 V range).

RESISTOR

STRING

REF(+)

REF(–)

2.5V

REF

INPUT

DAC

CLAMP/

DAC

ENABLE

RANGE

SELECT

UNI-VOUTX

0V TO 5V

2.5V TO 7.5V

5V TO 10V

Figure 44. Unipolar DAC Architecture Block Diagram

Table 17. Unipolar DAC Voltage Offset Ranges

Range (V)

0x000

0xFFF

VOFFSET (V)

0 to 5

0 V

2 V × VREFIN

2.5 to 7.5

VREFIN

3 V × VREFIN

2.5

5 to 10

2 V × VREFIN

4 V × VREFIN

DAC Enabling and Clamping

On power-up, the DAC outputs default to their clamp values

(see Table 18). All DACs can be enabled and disabled/clamped

via the DAC enable register (common to all pages).

Table 18. Clamp Values

DAC Output

Clamp Value

UNI-VOUT0

0 V

UNI-VOUT1

0 V

UNI-VOUT2

0 V

UNI-VOUT3

0 V

BI-VOUT0

−3 × VCLAMP0

BI-VOUT1

−3 × VCLAMP0

BI-VOUT2

−3 × VCLAMP1

BI-VOUT3

−3 × VCLAMP1

All DACs (bipolar DACs only on power-up) can be set to clamp

using the digital SLEEP0 and SLEEP1 pins. The DAC outputs

controlled by the digital SLEEP0 and SLEEP1 pins are selectable by

writing to the corresponding sleep bit in the DAC snooze/SLEEPx

pin register (see Table 45) in the configuration page. When the

SLEEPx pin is pulled active, the corresponding unipolar and

bipolar DACs associated with the pin are forced into clamp.

Clamping does not clear the DAC output register value, making

it possible to return to the same voltage as before the clamp

event. While in clamp mode, the DAC registers can be updated.

When a SLEEPx pin is used, a snooze function is available that

clears the DAC registers and requires an additional write to the

DAC enable register to wake up the DAC after clearing the clamp

condition.

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