AD7293 datasheet(15/79 Pages) AD

15 / 79 page

Data Sheet

AD7293

Rev. D | Page 15 of 79

Pin Number

Mnemonic

Description

DGND

Digital Ground. DGND is the ground reference point for all digital circuitry. Refer all digital

signals to DGND. Connect both the DGND and AGND pins to the ground plane of the system.

VDRIVE

Drive Voltage Reference Level of the SPI Bus from 1.7 V to 5.5 V.

DVDD

Digital Supply Voltage from 4.5 V to 5.5 V.

DACVDD-UNI

DAC Positive Supply Pin for the Unipolar DAC Output Amplifiers on UNI-VOUT0, UNI-VOUT1,

UNI-VOUT2, and UNI-VOUT3.

15, 16, 18, 19

UNI-VOUT0, UNI-VOUT1,

UNI-VOUT2, UNI-VOUT3,

Unipolar DAC Outputs. The clamp and power-on reset voltage for these DACs is 0 V.

17, 22, 35, 43

AGND

Analog Ground. Connect both the AGND and DGND pins to the ground plane of the system.

VREFIN

Reference Input to the Device. Connect this pin to an external reference voltage, or tie this

pin to VREFOUT.

VREFOUT

2.5 V Reference Output. Connect to VREFIN to operate in internal reference mode. An optional

10 nF capacitor is recommended between the reference output and AGND for noise filtering.

23, 24, 27, 28

BI-VOUT0, BI-VOUT1,

BI-VOUT2, BI-VOUT3

Bipolar DAC Outputs in Open-Loop Mode and Integrator Outputs in Closed-Loop Mode. The

clamp and power-on reset voltage for these DACs is dictated by the VCLAMPx pins.

AVSS

DAC Negative Supply Pin for the BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3 DAC Output

Amplifiers.

DACVDD-BI

Analog Supply Pin for BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3. Connect AVDD and DACVDD-BI to

the same potential.

VCLAMP1

Power-On Reset and Clamp Voltage for BI-VOUT2 and BI-VOUT3.

VCLAMP0

Power-On Reset and Clamp Voltage for BI-VOUT0 and BI-VOUT1.

31, 33, 36, 38

RS3−, RS2−, RS1−, RS0−

Negative Connection for External Shunt Resistors.

32, 34, 37, 39

RS3+, RS2+, RS1+, RS0+

Positive Connection for External Shunt Resistors.

PA_ON

Power Amplifier On. This pin drives an external, positive channel metal oxide semiconductor

(PMOS) switch capable of turning on/off the drain current to a PA transistor. The maximum

voltage is set by PAVDD and limited to AVSS + 60 V. The power amplifier is turned on when the

output is low. The AVSS and AVDD supply alarms can be configured to automatically trigger

PA_ON. An alert condition can be configured to trigger PA_ON. Additionally, PA_ON can be

turned on/off by issuing a register write.

PAVDD

Power Supply for the PA_ON Control Signal. This pin is limited to 4 V to AVSS + 60 V.

REFADC

Internal ADC Reference Voltage. The output at this pin is half the reference value (VREFIN),

1.25 V. Connect decoupling capacitors to this pin to decouple the reference buffer. For best

performance, connect a 4.7 µF compensation capacitor between REFADC and AGND. For

stability, the amplifier requires a minimum capacitance of 220 nF (X7R/C0G ceramic)

connected between REFADC and AGND, located as close to the AD7293 as possible (no more

than 1 Ω of interconnect resistance).

AVDD

Supply Voltage for All of the Analog Circuitry on the AD7293. The operating range is 4.5 V to

5.5 V. Connect AVDD and DACVDD-BI to the same potential.

45 to 48

VIN3, VIN2, VIN1, VIN0

ADC Analog Inputs. Unused inputs must not be left floating. The input range of these pins is

49, 50, 51, 52

D1−, D1+, D0−, D0+

Temperature Sensor Analog Inputs. Connect these pins to the external temperature sensing

transistor. Tie these pins to AGND if unused.

GPIO3/ALERT0

General-Purpose Input/Output 3 Pin (GPIO3, Default).

Alert 0 Pin (ALERT0). When ALERT0 is configured as an alert, this pin acts as an out of range

indicator. Open-drain output whether in GPIO mode or alert mode. The polarity of this pin is

GPIO2/BUSY

General-Purpose Input/Output 2 Pin (GPIO2, Default).

Busy Pin (BUSY). When BUSY is configured as a busy output, this pin becomes active when a

conversion is in progress. Open-drain output whether in GPIO mode or busy mode. The

polarity of this pin is register selectable. A pull-up resistor connected to VDRIVE is required.

GPIO1/CONVST

General-Purpose Input/Output 1 Pin (GPIO1, Default). This pin is an open-drain output in

GPIO mode. The polarity of this pin is register selectable.

ADC External Convert Start Input Pin (CONVST). CONVST triggers conversions via this pin. The

CONVST pin is useful for synchronizing the ADC sampling instant with an external source. A

pull-up resistor connected to VDRIVE is required in GPIO mode or if unused.

AD7293 Datasheet(PDF) 15 Page - Analog Devices

AD7293 Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL