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AD7293

Data Sheet

Rev. D | Page 78 of 79

threshold voltage is not exceeded in the event of AVDD voltage

supply failure.

The on-chip bipolar DAC clamping circuitry ensures that the

four bipolar outputs are set to their clamp value on power-up,

and the DACs can be triggered to clamp by the external SLEEPx

pins at any stage by the user.

The voltage monitoring of the supply voltages can help to

quickly detect any system issues. The bipolar DAC output

monitoring can be useful in closed-loop mode to sense the

voltage output controlling the PA gate. Monitoring of the RSx+

pins voltages helps in detecting issues on the high side of the

sense resistor.

To adhere to radio standards, it may be necessary to control the

rate at which the PA gain changes. A ramp register is available

that allows the user to control the slew rate of the DAC in

closed-loop mode. Additionally, a closed-loop sequence is

provided in the Closed-Loop Sequencing section to ensure the

protection of the power amplifier from an overvoltage.

LOOP COMPONENT SELECTION

To select the loop component, use the following conditions:

RS ≤ 0.2/IDS(MAX)

RS ≤ τI/(52.5 μs × gm(MAX))

τG ≤ τI/(25 × gm(MAX) × RS)

τS ≤ (1/10) × τG

where:

RS is the value of the current sense resistor in ohms.

IDS(MAX) is the PA drain current at the maximum required PA

gain in amperes.

τI is the integrator time constant (default value = 840 μs) in

seconds.

gm(MAX) is the PA transconductance at the maximum required PA

gain in Siemens.

τG is the gate filter time constant in seconds.

τS is the current sense filter time constant in seconds.

To optimize the loop response from this point, the RS, τI, τG, and

τS values can be adjusted (see Table 116).

Table 116. RS, τI, τG, and τS Adjustment Values

Parameter

Benefit of Increasing

Benefit of Decreasing

Setpoint resolution

increased, improved

dynamic range, and

faster settling

Reduced overshoot,

reduced power

dissipation, and allows

higher τG and τS

τI

Reduced overshoot,

allows higher τG and τS

Faster settling

τG

Reduced noise from

current control loop

Reduced overshoot,

allows lower τI

τS

Improved filtering of

disturbances at current

sense input

Reduced overshoot,

allows lower τI

When setting τG, do not exceed the maximum load capacitance

specification (10 nF when RG = 0 Ω, and 1 μF when RG = 5 Ω).

Include the PA gate capacitance in the calculation.

τS

τG

τI

VPP

AD7293

RSx+

RSx–

DAC

BI-VOUTx

Figure 60. Loop Component Selection and Filtering

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