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Data Sheet

AD7293

Rev. D | Page 29 of 79

Closed-Loop Integrator Programmable Voltage Limit

The AD7293 ADC can monitor the voltage at the output of the

integrator by writing to a register (Register 0x23) from the

configuration page (see Table 46).

The integrator voltage limit feature allows the user to set upper

and lower limits on the integrator output voltage in closed-loop

mode of operation. When the integrator limit is active, the

integrator pauses and the output voltage holds constant. The

polarity of the error amplifier (comparison between measured

current and target current) determines when it is safe to deactivate

the soft limit. For example, a lower target current is programmed,

which makes the integrator output decrease, making it safe to

deactivate the integrator limit.

It is recommended to use the hysteresis registers (see Table 66

and Table 69) to avoid the device switching in and out of the

alert condition close to the limits. Additionally, the integrator

limit feature can be made a function of the upper/lower limits

only by ignoring the polarity of the error amplifier (via D2 of

the general register (Register 0x14) from the configuration page).

The integrator limit feature does not enable by default and can

be enabled by writing to the integrator limit and closed-loop

control register (Register 0x28).

Closed-Loop Range Upper Voltage Limit

An analog circuit within the output integrator creates a

hardware range upper limit on the output voltage of either 0 V or

1 V, as shown in Table 19. If the hardware limiting circuitry is

active, an alert appears on the INTLIMITx and AVSS/AVDD alert

Alert Register (Register 0x1A) section.

Table 19. Closed-Loop Range Upper Voltage Limit

Operation

Bipolar DAC Range (V)

Range Limit

Open Loop

X = don’t care

Off

Closed Loop

0 to +5

Off

Closed Loop

−4 to +1

On (1 V)

Closed Loop

−5 to 0

On (0 V)

DIGITAL INPUT/OUTPUT REGISTERS

Eight pins can be set as GPIOs or can perform various digital

functions. Three registers located on the configuration page set

up the functionality of the GPIO interface. GPIO0 to GPIO3

default to the GPIOs on power-up. ALERT1, SLEEP0, SLEEP1,

and LDAC default to digital functions on power-up.

The GPIO register (Register 0x5) configures the GPIOs in the

device. In GPIO mode, and with the output drivers enabled, the

GPIO outputs reflect the value written to this register. In

functional mode, any write to this register has no effect on the

GPIO outputs. See the GPIO Register (Register 0x05) section.

The digital output enable register (Register 0x11) enables the

output drivers of the GPIO pins; therefore, when using one of

the pins as an output in GPIO mode or functional mode (for

alerts and busy), the corresponding bit must be set. See the

Digital Output Enable Register (Register 0x11) section.

The digital input/output function register (Register 0x12) allows the

user to put the relevant pin into GPIO mode or functional mode.

See the Digital Input/Output Function Register (Register 0x12)

section.

The digital functional polarity register (Register 0x13) sets the

polarity of the digital input/output pins in functional mode only.

The associated input/output signal can be made active low or

active high. See the Digital Functional Polarity Register

(Register 0x13) section.

LOAD DAC (LDAC PIN)

The AD7293 DACs have doubled buffered interfaces consisting

of two banks of registers: input registers and DAC registers. The

user can write to any combination of the input registers. If the

load bit is held high when writing to a DAC, updates to the

DAC register are controlled by the LDAC pin.

Instantaneous DAC Updating (Asynchronous)

In this operation mode, the SPI data is clocked into the DAC

input register on the rising edge of the SCLK. The output register is

updated, and the output begins to change. Instantaneous DAC

updating is only applicable when the load bit is not set when

writing to the DAC register. Hold the LDAC pin in its false state.

Deferred DAC Updating (Synchronous)

In this mode, the SPI data is clocked into the DAC input registers

on the rising edge of the SCLK. However, the update of the

output registers can be blocked during the SPI write by setting

the load bit. The output registers can be synchronously updated

(data is transferred from the DAC input register to the DAC

output register) by taking the LDAC pin to its true state.

ALERTS AND LIMITS

The high and low limit pages comprise registers that set the

high and low alerts for the analog input channels, the current

sensors, the internal supply monitoring channels, the internal

bipolar DAC monitoring channels, and the RSx+ monitoring

channels. Each register is 16 bits in length; values are 12-bit, left

justified (padded with 0s as the four LSBs). On power-up, the

low limit registers contain all zeros, whereas the high limit

registers contain 0xFFF0.

The alert high limit registers on Page 0x04 (High Limit 0) and

Page 0x05 (High Limit 1) store the upper limit that activates an

alert (see the High Limit 0 (Page 0x04) section and the High Limit

1 (Page 0x05) section). If the conversion result is greater than the

value in the alert high limit register, an alert triggers. The alert low

registers on Page 0x06 (Low Limit 0) and Page 0x07 (Low Limit 1)

store the low limit that activates an alert (see the Low Limit 0

(Page 0x06) section and the Low Limit 1 (Page 0x07) section). If

the conversion result is less than the value in the alert low limit

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