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AD7293 Datasheet(PDF) 43 Page - Analog Devices

Part # AD7293
Description  12-Bit Power Amplifier Current Controller with ADC, DACs, and Temperature and Current Sensors
PDF  79 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7293 Datasheet(HTML) 43 Page - Analog Devices

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Data Sheet
AD7293
Rev. D | Page 43 of 79
Bit Number(s)
Bit Name
Description
D4
BI-VOUT0
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D3
UNI-VOUT3
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D2
UNI-VOUT2
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D1
UNI-VOUT1
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D0
UNI-VOUT0
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
Table 46. RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23)
Bit Number(s)
Bit Name
Description
[D15:D12]
Reserved
Reserved
D11
RS3+MON
0: disable background conversions (default)
1: enable background conversions
D10
RS2+MON
0: disable background conversions (default)
1: enable background conversions
D9
RS1+MON
0: disable background conversions (default)
1: enable background conversions
D8
RS0+MON
0: disable background conversions (default)
1: enable background conversions
D7
BI-VOUT3MON
0: disable background conversions (default)
1: enable background conversions
D6
BI-VOUT2MON
0: disable background conversions (default)
1: enable background conversions
D5
BI-VOUT1MON
0: disable background conversions (default)
1: enable background conversions
D4
BI-VOUT0MON
0: disable background conversions (default)
1: enable background conversions
D3
AVSS
0: disable background conversions (default)
1: enable background conversions
D2
DACVDD-BI
0: disable background conversions (default)
1: enable background conversions
D1
DACVDD-UNI
0: disable background conversions (default)
1: enable background conversions
D0
AVDD
0: disable background conversions (default)
1: enable background conversions
Table 47. Integrator Limit and Closed-Loop (CL) Control Register (Register 0x28)
Bit Number(s)
Bit Name
Description
[D15:D12]
Reserved
Reserved
D11
INT_CL_LIMIT_CH3
0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D10
INT_CL_LIMIT_CH2
0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D9
INT_CL_LIMIT_CH1
0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D8
INT_CL_LIMIT_CH0
0: no control (default)
1: the soft closed-loop limit for the channel is enabled
[D7:D4]
Reserved
Reserved



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