AD7293 datasheet(25/79 Pages) AD

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Data Sheet

AD7293

Rev. D | Page 25 of 79

For RF applications, the use of high Q capacitors functioning as

a filter protects the integrity of the measurement. Connect these

capacitors between the base and the emitter, as close to the

external device as possible. However, large capacitances affect

the accuracy of the temperature measurement; therefore, the

recommended maximum capacitor value is 100 pF. In most

cases, a capacitor is not required; the selection of any capacitor

is dependent on the noise frequency level.

The AD7293 automatically cancels out the effect of parasitic,

base, and collector resistance on the temperature reading. This

cancelation gives a more accurate result, without the need for

any user characterization of the parasitic resistance. The AD7293

can compensate for up to 4 kΩ series resistance typically.

2N3904

NPN

AD7293

Dx+

Dx–

10pF

Figure 40. Measuring Temperature Using a NPN Transistor

10pF

2N3906

PNP

AD7293

Dx+

Dx–

Figure 41. Measuring Temperature Using a PNP Transistor

Table 15. Temperature Sensor Data Format

Temperature

(°C)

TSENSEx Result Registers (Page 0x00,

−40

0110 1100 0000

−25

0111 0011 1000

−10

0111 1011 0000

−0.125

0111 1111 1111

1000 0000 0000

+0.125

1000 0000 0001

+10

1000 0101 0000

+25

1000 1100 1000

+50

1001 10 01 0000

+75

1010 0101 1000

+100

1011 0010 0000

+125

1011 1110 1000

INTERNAL CHANNEL MONITORING

The ADC can internally read the outputs of the four bipolar

DACs, AVDD, DACVDD-UNI, DACVDD-BI, AVSS, and the voltage on

the RS0+ to RS3+ pins in the background. A sequencer is

available that allows multiple channels to be converted in a

predetermined sequence.

The ADC is used in its single-ended mode. The LSB size varies

with the different supply monitoring registers. AVDD and DACVDD-BI

are divided by 5, and DACVDD-UNI is divided by 20 to scale within

the 0 V to REFADC range. AVSS is divided by 8 and level shifted

to within a −7.5 V to +2.5 V range, where 0x000 equates to

approximately −7.5 V, and 0xFFF equates to approximately

+2.5 V. REFADC = 1.25 V. For RSx+MON (internal monitoring of

the voltage on the RS0+ to RS3+ pins), divide by 50 to scale

them to the 0 V to REFADC range. For BI-VOUTxMON, divide by 8

and level shift within a −5 V to +5 V range, where 0x000

equates to approximately −5 V, and 0xFFF equates to approx-

imately +5 V. The RSx+MON monitor result registers store the 12-bit

ADC results for the current sense supply channels (see Figure 42).

12-BIT

SAR ADC

MUX

0V TO +1.25V

0V TO +62.5V

RS0+MON

0V TO +1.25V

0V TO +62.5V

RS1+MON

0V TO +1.25V

0V TO +62.5V

RS2+MON

0V TO +1.25V

0V TO +62.5V

RS3+MON

0V TO +1.25V

–5V TO +5V

BI-VOUT0MON

0V TO +1.25V

–5V TO +5V

BI-VOUT1MON

0V TO +1.25V

–5V TO +5V

BI-VOUT2MON

0V TO +1.25V

–5V TO +5V

BI-VOUT3MON

0V TO +1.25V

0V TO +6.25V

DACVDD-BI

0V TO +1.25V

0V TO 25V

DACVDD-UNI

0V TO +1.25V

–7.5V TO +2.5V

AVSS

0V TO +1.25V

0V TO +6.25V

AVDD

Figure 42. Internal Channel Monitoring

DAC OPERATION

The AD7293 contains eight 12-bit DACs, four bipolar DACs,

and four unipolar DACs. These provide digital control with 12 bits

of resolution combined with offset range select registers and a

2.5 V internal reference. The DAC core is a 12-bit string DAC. The

resistor string structure consists of a string of resistors, each of

Value R. The code loaded to the DAC register determines at

which node on the string the voltage is tapped off to be fed into

the output amplifier. When one of the switches connecting the

string to an amplifier is closed, the voltage is tapped off. This

architecture is inherently monotonic and linear. The eight DACs

are split into two groups based on their output range.

Bipolar DACs

The bipolar DACs (BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3)

can be configured through the offset range registers to 0 V to

+5 V, −5 V to 0 V, or −4 V to +1 V (see Table 85).

Writing to these register addresses sets the 12-bit DAC output

voltage. There is also a load bit and a copy bit (see Table 27).

If the load bit is set to 1, the device waits for LDAC to become

active before loading the voltage codes onto the DACs rather than

immediately after the write operation. If the copy bit is set to 1

when writing to a bipolar DAC register, it sets all bipolar DAC

registers to the same value in open-loop mode only.

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