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AD7293

Data Sheet

Rev. D | Page 62 of 79

Supply and BI-VOUTxMON Alert Register (Register 0x18)

This 16-bit register stores the AVDD, DACVDD-UNI, DACVDD-BI,

AVSS, BI-VOUTxMON high and low alerts. When 1 is written to any

of the register bits, this bit clears, removing the corresponding

alert.

RSx+MON Alert Register (Register 0x19)

This 16-bit register stores the RSx+ high and low alerts. When 1

is written to any of the register bits, this bit clears, removing the

corresponding alert.

INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A)

This 16-bit register stores the closed-loop integrator limit active

status and AVSS/AVDD alarm status.

Table 94. Supply and BI-VOUTxMON Alert Register (Register 0x18), Bit D15 to Bit D8

D15

D14

D13

D12

D11

D10

BI-VOUT3MON high

BI-VOUT2MON high

BI-VOUT1MON high

BI-VOUT0MON high

AVSS high

DACVDD-BI high

DACVDD-UNI high

AVDD high

Table 95. Supply and BI-VOUTxMON Alert Register (Register 0x18), Bit D7 to Bit D0

BI-VOUT3MON low

BI-VOUT2MON low

BI-VOUT1MON low

BI-VOUT0MON low

AVSS low

DACVDD-BI low

DACVDD-UNI low

AVDD low

Table 96. RSx+MON Alert Register (Register 0x19)

MSB

LSB

[D15:D12]

D11

D10

[D7:D4]

Reserved

RS3+MON high

RS2+MON high

RS1+MON high

RS0+MON high

Reserved

RS3+MON low

RS2+MON low

RS1+MON low

RS0+MONlow

Table 97. INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A)

MSB

LSB

[D15:D12]

D11

D10

[D7:D1]

Reserved

INTLIMIT3 high

INTLIMIT2 high

INTLIMIT1 high

INTLIMIT0 high

Reserved

AVSS/AVDD alarm

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