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AD7293 Datasheet(PDF) 9 Page - Analog Devices |
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AD7293 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 79 page  Data Sheet AD7293 Rev. D | Page 9 of 79 CURRENT SENSOR AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, gain = 6.25, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments CURRENT SENSE RSx+ = AVDD to AVSS + 60 V Common-Mode Input Voltage Range 4 60 V AVSS = 0 V 4 55 V AVSS = −5 V Differential Input Voltage Range −200 +200 mV Gain = 6.25, for gain settings, see Table 44 Gain Error ±0.1 ±0.7 % Gain Error Temperature Coefficient −16 ppm/°C Offset Error (Referred to Input, RTI) ±200 µV Offset Error Drift 1 µV/°C DC Common-Mode Rejection 100 140 dB RSx+1 Pin Input Current 105 µA RSx−1 Pin Input Current 10 nA Differential Input Resistance2 700 kΩ 1 Where x is 0, 1, 2, or 3. 2 Guaranteed by design and characterization; not production tested. CLOSED-LOOP SPECIFICATIONS AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted. Power amplifier transconductance = 1 S to 5 S, and external gate filter time constant (τG) = 5 µs to 50 µs. Table 5. Parameter Min Typ Max Unit Test Conditions/Comments NORMAL OPERATION1, 2 Setpoint Resolution 12 Bits Equivalent to 200 mV/4096 = 49 µV at the current sense input Sense Resistor Voltage Range 0 200 mV Setpoint Gain Error ±0.5 % Setpoint Offset Error (RTI) ±100 µV Referred to current sense input; see Figure 31 Integrator Time Constant3 840 µs Programmable; see Table 50 Closed-Loop Update Rate3 59.6 kHz Capacitive Load Stability 1 µF 5 Ω series resistance Closed-Loop to Clamp Settling Time 1 µs Within ±10% Bipolar Closed-Loop Output Range AVSS AVDD V See the Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) section Integrator Programmable Voltage Limit Resolution 2.5 mV See the Closed-Loop Integrator Programmable Voltage Limit section START SEQUENCING PA_ON CONTROL2 PA_ON Pin Output Voltage AGND PAVDD V PA_ON Off State Enable 500 µs Measured from AVSS failure event, CL = 1 nF 500 µs Measured from SLEEP0 or SLEEP1 pin, 0 to 1 transition, CL = 1 nF PA_ON On State Enable 500 µs Measured from SLEEP1 to SLEEP0 transition, CL = 1 nF PA_ON Short-Circuit Current ±10 mA PA_ON Resistance 250 Ω AVDD/AVSS ALARM AVDD Alarm Threshold 3.2 3.6 3.9 V AVSS Alarm Threshold −3.8 −4.1 −4.4 V 1 Power amplifier characteristic dependent. 2 Guaranteed by design and characterization; not production tested. 3 Expressed as a function of the internal oscillator frequency. |
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