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AD7293 Datasheet(PDF) 11 Page - Analog Devices |
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AD7293 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 79 page  Data Sheet AD7293 Rev. D | Page 11 of 79 TIMING CHARACTERISTICS SPI Serial Interface AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 2.7 V to 16 V, AVSS = 0 V, RSx+ = AVDD to 55 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external, VDRIVE = 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Table 7. Limit at TMIN/TMAX Parameter Description VDRIVE = 1.7 V to 2.7 V VDRIVE = 2.7 V to 5.5 V Unit fSCLK Frequency of serial read clock1 8 15 MHz max t1 SCLK period 150 66.67 ns min t2 SCLK low 40 26 ns min t3 SCLK high 40 26 ns min t4 CS falling edge to SCLK rising edge 5 5 ns min t5 DIN setup time to SCLK rising edge 10 10 ns min t62 DIN hold time after SCLK rising edge 10 10 ns max t7 Last SCLK rising edge to CS rising edge 5 5 ns min t8 CS high 12 10 ns min t93 CS rising edge to next SCLK rising edge 1 1 ns min t10 SCLK falling edge to CS falling edge 1 1 ns min t11 SCLK falling edge to output data valid delay time from high impedance4 60 30 ns max t12 SCLK falling edge to output data valid delay time4 60 30 ns max t13 Last SCLK falling edge to DOUT high impedance4 20 20 ns typ t14 CS rising edge to DOUT high impedance4 25 15 ns max 1 DOUT loaded with 10 pF for DOUT timing specifications. 2 Time required for the output to cross 0.2 × VDRIVE and 0.8 × VDRIVE when VDRIVE < 2.7 V; time required for the output to cross 0.3 × VDRIVE and 0.7 × VDRIVE when 2.7 ≤ VDRIVE ≤5.5 V. 3 Guaranteed by design and characterization; not production tested. 4 MISO speed set to maximum in the general register. Asynchronous Inputs AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 2.7 V to 16 V, AVSS = 0 V, RSx+ = AVDD to 55 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external, VDRIVE = 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Table 8. Limit at TMIN/TMAX Parameter Description VDRIVE = 1.7 V to 2.7 V VDRIVE = 2.7 V to 5.5 V Unit t151 Minimum LDAC pulse width 90 90 ns min t16 Minimum CONVST pulse width 90 90 ns min t17 Minimum IS BLANK pulse width 90 90 ns min t18 Minimum RESET pulse width 90 90 ns min 1 Guaranteed by design and characterization; not production tested. |
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