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STAC9752 Datasheet(PDF) 18 Page - Integrated Device Technology

Part # STAC9752
Description  TWO-CHANNEL, 20-BIT, AC??7 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
PDF  95 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

STAC9752 Datasheet(HTML) 18 Page - Integrated Device Technology

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STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
18
STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
2.2.5.
Data Setup and Hold
(50 pF external load)
Figure 5. Data Setup and Hold Timing
2.2.6.
Signal Rise and Fall Times
(BIT_CLK: 75 pF external load; from 10% to 90% of Vdd)
(SDATA_IN: 60 pF external load; from 10% to 90% of Vdd)
Figure 6. Signal Rise and Fall Times Timing
Table 2. Common Clocks and Sources
Clock Source
Clock Frequency
XTAL
24.576 MHz
BIT_CLK
12.288 MHz
VGA
14.31818 MHz
Digital Video
27 MHz
USB
48 MHz
Parameter
Symbol
Min
Typ
Max
Units
Setup to falling edge of BIT_CLK
Tsetup
10
-
-
ns
Hold from falling edge of BIT_CLK
Thold
10
-
-
ns
Output Valid Data from rising edge of BIT_CLK
tco
-
-
15
ns
Note:
Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK rise time
Triseclk
-
-
6
ns
BIT_CLK fall time
Tfallclk
-
-
6
ns
SDATA_IN rise time
Trisedin
-
-
6
ns
SDATA_IN fall time
Tfalldin
-
-
6
ns
BIT_CLK
T
hold
T
setup
SDATA_OUT
SDATA_IN
SYNC
tco
V
ih
V
il
V
oh
V
ol
BIT_CLK
SDATA_IN
Tfallclk
Triseclk
Trisedin
Tfalldin



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