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STAC9752 Datasheet(PDF) 77 Page - Integrated Device Technology |
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STAC9752 Datasheet(HTML) 77 Page - Integrated Device Technology |
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77 / 95 page ![]() STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING IDT™ 77 STAC9752/9753 REV 3.3 1206 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4.10. Analog Current Adjust (72h) To unlock Register 72h, write 0xABBA to Register 70h. Default: 0000h 8.4.11. EAPD Access Register (74h) Default: 0800h 3 0 RESERVED RESERVED 2 0 MIC GAIN VAL Adds +10dB gain to the selected MIC input. Use in conjunction with BOOSTEN (Reg. 0Eh;D6) BOOSTEN MICGAINVAL 0 0 = 0 dB 0 1 = 10 dB 1 0 = 20 dB 1 1 = 30 dB 1 0 SPLYOVR_EN Supply Override bit allows override of the supply detect. 0 = No override on supply detect 1 = Override supply detect with bit 0 0 0 SPLYOVR_VA L Supply Override Value provides the analog voltage operation values. 0 = Force 3.3 v operation 1 = Force 5 V operation D15 D14 D13 D12 D11 D10 D9 D8 RESERVED D7 D6 D5 D4 D3 D2 D1 D0 INT APOP RESERVED Bit(s) Reset Value Name Description 15:8 0 Reserved Reserved 7 0 INT_APOP 0 = Anti Pop Enabled 1 = Anti Pop Disabled The STAC9752/9753 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the CODEC is powered on and off. This function is accomplished by delaying the charge/discharge of the VREF capacitor (Pin 27). A CVREF value of 1 µF will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the CODEC outputs are enabled. The delay will be extended to 30 seconds if a CVREF value of 10 µF is used. The CODEC outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. The Anti Pop bit allows this delay circuit to be bypassed for rapid production testing. Any external component anti-pop circuit is unaffected by the internal circuit. 6:0 0 Reserved Reserved D15 D14 D13 D12 D11 D10 D9 D8 EAPD RESERVED EAPD_OEN RESERVED D7 D6 D5 D4 D3 D2 D1 D0 RESERVED INTDIS GPIOACC GPIOSLT12 Bit(s) Reset Value Name Description |
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