STAC9752 datasheet(31/95 Pages) IDT

31 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

valid and non-valid slots? Each possible method brings with it different FIFO requirements. To

achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different man-

ufacturers, it is necessary to standardize the scheme for at least one side of the AC-Link so that the

FIFO requirements will be common to all designs. The CODEC side of the AC-Link is the focus of

this standardization.

The new standard approach calls for the addition of “on demand” slot request flags. These flags are

passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time

the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)

in a given audio input frame, it knows that it must pass along the next PCM sample for the corre-

sponding slot(s) in the AC-Link output frame that immediately follows.

The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to

1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:

Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate

Registers 2Ch through 34h.

Enables the on demand CODEC-to-Controller signaling protocol using SLOTREQ bits that

becomes necessary when a DAC’s sample rate varies from the 48 KHz AC-Link serial frame

rate.

The table below summarizes the behavior:

Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should NOT be

used.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-Link output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current

AC-Link input frame signal which active output slots require data from the AC‘97 Digital Controller in

the next audio output frame. An active output slot is defined as any slot supported by the CODEC

that is not in a power-down state. For fixed 48KHz operation the SLOTREQ bits are always set

active (low) and a sample is transferred in each frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame.

The VRM (Variable Rate Microphone Audio) bit in the Extended Audio Status and Control Register

controls the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.

5.2.2.1.

SLOTREQ Behavior and Power Management

SLOTREQ bits for fixed rate, powered down, and all unsupported Slots should be driven low (zero)

for maximum compatibility with the original AC'97 Component Specification. When a DAC channel is

powered down, it disappears completely from the serial frame: output tag and slot are ignored, and

the SLOTREQ bit is absent (forced to zero).

When the Controller wants to power-down a channel, all it needs to do is:

Table 6. VRA Behavior

AC‘97 Functionality

VRA = 0

VRA = 1

SLOTREQ bits

always 0 (data each frame)

0 or 1 (data on demand)

sample rate registers

forced to 48KHz

writable

STAC9752 Datasheet(PDF) 31 Page - Integrated Device Technology

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