STAC9752 datasheet(38/95 Pages) IDT

38 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY

indicates valid Status Address Port data (Control Register Index). The CODEC should only set

SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-

ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the

Slot 1 tag bit.

SLOTREQ bits are always 0 in the following cases:

•

fixed rate mode (VRA = 0)

•

inactive (powered down) ADC channel

SLOTREQ bits are only set to 1 by the CODEC in the following case:

•

Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48 KHz ADC

sample rate AND CODEC does not need a sample

5.4.3.

Slot 2: Status Data Port

The status data port delivers 16-bit control register read data.

If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0 by AC‘97.

5.4.4.

Slot 3: PCM Record Left Channel

Audio input frame slot 3 is the left channel output of STAC9752/9753 input MUX, post-ADC.

STAC9752/9753 ADCs are implemented to support 20-bit resolution.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.5.

Slot 4: PCM Record Right Channel

Audio input frame slot 4 is the right channel output of STAC9752/9753 input MUX, post-ADC.

STAC9752/9753 ADCs are implemented to support 20-bit resolution.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.6.

Slot 5: Modem Line 1 ADC

Audio input frame slot 5 is not used by the STAC9752/9753 and is always stuffed with 0.

5.4.7.

Slot 6 - 9: ADC

The left and right ADC channels of the STAC9752/9753 may be assigned to slots 6&9 by Register

6Eh.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

Table 10. Status Data Port Bit Assignments

Bit

Description

Comments

19:4

Control Register Read Data

Stuffed with 0 if tagged “invalid”

3:0

Reserved

Stuffed with 0

STAC9752 Datasheet(PDF) 38 Page - Integrated Device Technology

STAC9752 Datasheet(HTML) 38 Page - Integrated Device Technology

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