STAC9752 datasheet(16/95 Pages) IDT

Part #	STAC9752

Description	TWO-CHANNEL, 20-BIT, AC??7 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

PDF	95 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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16 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

2.2.

AC Timing Characteristics

ambient = 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3 V ± 5%, AVss=DVss=0 V; 75 pF external

load for BIT_CLK and 60 pF external load for SDATA_IN)

2.2.1.

Cold Reset

Figure 2. Cold Reset Timing

Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.

2.2.2.

Warm Reset

Figure 3. Warm Reset Timing

Parameter

Symbol

Min

Typ

Max

Units

RESET# active low pulse width

Tres_low

1.0

µs

RESET# inactive to SDATA_IN or BIT_CLK active delay

Tri2actv

RESET# inactive to BIT_CLK startup delay

Trst2clk

0.01628

400

µs

BIT_CLK active to RESET# asserted (Not shown in diagram)

Tclk2rst

0.416

µs

Parameter

Symbol

Min

Typ

Max

Units

SYNC active high pulse width

Tsync_high

1.0

1.3

µs

SYNC inactive to BIT_CLK startup delay

Tsync2clk

162.8

Tres_low

Trst2clk

RESET#

BIT_CLK

SDATA_IN

Ttri2actv

Tsync_high

Tsync_2clk

SYNC

BIT_CLK

STAC9752 Datasheet(PDF) 16 Page - Integrated Device Technology

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