STAC9752 datasheet(19/95 Pages) IDT

19 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

2.2.7.

AC-Link Low Power Mode Timing

Figure 7. AC-Link Low Power Mode Timing

2.2.8.

ATE Test Mode

Figure 8. ATE Test Mode Timing

Note:

All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge

of RESET# causes the STAC9752/9753 AC-Link outputs to go high-impedance which is suitable for ATE in circuit testing.

Once the test mode has been entered, the STAC9752/9753 must be issued another RESET# with all AC-Link signals low

to return to the normal operating mode.

The pound sign (#) appended to the end of a signal name denotes that the signal is active low.

Parameter

Symbol

Min

Typ

Max

Units

End of Slot 2 to BIT_CLK, SDATA_IN low

Ts2_pdown

1.0

µs

Parameter

Symbol

Min

Typ

Max

Units

Setup to trailing edge of RESET# (also applies to SYNC)

Tsetup2rst

15.0

Rising edge of RESET# to Hi-Z delay

Toff

25.0

BIT_CLK

SDATA_IN

Note: BIT_CLK not to scale

Ts2_pdown

Don't care

Data PR4

Write to

0x20

Slot 2

Slot 1

SDATA_OUT

SYNC

Tsetup2rst

Hi-Z

Toff

RESET#

SDATA_OUT

SDATA_IN, BIT_CLK

STAC9752 Datasheet(PDF) 19 Page - Integrated Device Technology

STAC9752 Datasheet(HTML) 19 Page - Integrated Device Technology

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