STAC9752 datasheet(6/95 Pages) IDT

6 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

LIST OF TABLES

Table 1. Clock Mode Configuration ............................................................................................................... 17

Table 2. Common Clocks and Sources ......................................................................................................... 18

Table 3. Recommended CODEC ID strapping ............................................................................................. 26

Table 4. AC-Link output slots (transmitted from the Controller) ..................................................................... 29

Table 5. The AC-Link input slots (transmitted from the CODEC) .................................................................. 30

Table 6. VRA Behavior .................................................................................................................................. 31

Table 7. Output Slot 0 Bit Definitions ............................................................................................................ 34

Table 8. Command Address Port Bit Assignments ........................................................................................ 35

Table 9. Status Address Port Bit Assignments .............................................................................................. 37

Table 10. Status Data Port Bit Assignments .................................................................................................. 38

Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................ 40

Table 12. Secondary CODEC Addressing: Slot 0 Tag Bits ........................................................................... 40

Table 13. AC-Link Slot Definitions ................................................................................................................. 41

Table 14. AC-Link Input Slots Dedicated To Audio ....................................................................................... 41

Table 15. Audio Interrupt Slot Definitions ...................................................................................................... 42

Table 16. Digital PC Beep Examples ............................................................................................................. 46

Table 17. Programming Registers ................................................................................................................. 47

Table 18. Extended Audio ID Register Functions .......................................................................................... 60

Table 19. AMAP compliant ............................................................................................................................ 63

Table 20. Hardware Supported Sample Rates .............................................................................................. 63

Table 21. Supported Jack and Microphone Sense Functions .......................................................................71

Table 22. Reg 68h Default Values ................................................................................................................. 73

Table 23. Gain or Attenuation Examples ....................................................................................................... 73

Table 24. Register 68h/Page 01h Bit Overview ............................................................................................. 73

Table 25. Sensed Bits (Outputs) ................................................................................................................... 75

Table 26. Sensed Bits (Inputs) ...................................................................................................................... 75

Table 27. Low Power Modes ......................................................................................................................... 80

Table 28. CODEC ID Selection .....................................................................................................................82

Table 29. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................83

Table 30. Test Mode Activation .....................................................................................................................84

Table 31. ATE Test Mode Operation ............................................................................................................. 84

Table 32. Digital Connection Signals ............................................................................................................. 86

Table 33. Analog Connection Signals ........................................................................................................... 87

Table 34. Filtering and Voltage References .................................................................................................. 88

Table 35. Power and Ground Signals ............................................................................................................ 88

STAC9752 Datasheet(PDF) 6 Page - Integrated Device Technology

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