STAC9752 datasheet(58/95 Pages) IDT

58 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.1.18.

Powerdown Ctrl/Stat (26h)

Default: 000Fh

Read / Write

Interrupt Enable

0 = Interrupt generation is masked.

1 = Interrupt generation is un-masked.

The driver should not un-mask the interrupt unless ensured by the

AC ‘97 controller that no conflict is possible with modem slot 12 -

GPI functionality. Some AC’97 2.2 compliant controllers will not

likely support audio CODEC interrupt infrastructure. In either case,

S/W should poll the interrupt status after initiating a sense cycle

and wait for Sense Cycle Max Delay to determine if an interrupting

event has occurred.

10:4

Read Only

RESERVED Bits not used, should read back 0

3:0

Read / Write

PG3:PG0

Page Selector

0h = Vendor Specific

1h = Page ID 01 (See Section 8.4 for additional information on the

Paging Registers)

Fh = Reserved Pages

This register is used to select a descriptor of 16 word pages

between registers 60h to 6Fh. Value 0h is used to select vendor

specific space to maintain compatibility with AC’97 2.2 vendor

specific registers.

System S/W determines implemented pages by writing the page

number and reading the value back. All implemented pages must

be consecutive. (i.e., page 2h cannot be implemented without page

1h).

These registers are NOT reset on RESET#.

D15

D14

D13

D12

D11

D10

EAPD

PR6

PR5

PR4

PR3

PR2

PR1

PR0

RESERVED

REF

ANL

DAC

ADC

Bit(s)

Reset Value

Name

Description

EAPD

1 = Forces EAPD pad to Vdd

0 = Forces EAPD pad to GND

PR6

0 = Headphone Amp powered up

1 = Headphone Amp powered down

PR5

0 = Digital Clk active

1 = Digital Clk disable.

PR4

0 = digital active

1 = Powerdown: PLL, AC-Link, Xtal oscillator ;

PR3

0 = VREF and VREFOUT are active

1 = VREF and VREFOUT are powered down, and PR2 is asserted in

analog block

PR2

0 = analog active

1 = all signal path analog is powered down

PR1

0 = DAC powered up

1 = DAC powered down

Bit(s) Reset Value

Access

Name

Description

STAC9752 Datasheet(PDF) 58 Page - Integrated Device Technology

STAC9752 Datasheet(HTML) 58 Page - Integrated Device Technology

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