STAC9752 datasheet(30/95 Pages) IDT

30 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.2.

AC-Link Serial Interface Protocol

The AC‘97 Controller signals synchronization of all AC-Link data transactions. The AC‘97 CODEC,

Controller, or external clock source drives the serial bit clock (BIT_CLK) onto AC-Link, which the

AC‘97 Controller then qualifies with a synchronization signal (SYNC) to construct audio frames.

SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at

12.288 MHz, provides the necessary clocking granularity to support 12 20-bit outgoing and incoming

time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of

AC-Link data (CODEC for outgoing data and Controller for incoming data) samples each serial bit on

the falling edges of BIT_CLK.

The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid

tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0

indicates that the corresponding time slot within the current audio frame has been assigned to a data

stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the

data (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit posi-

tions with 0 during that slot’s active time.

SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The

portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the

audio frame where SYNC is low is defined as the “Data Phase”.

Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that an

AC‘97 CODEC be implemented as a static design to allow its register contents to remain intact when

entering a power savings mode.

5.2.1.

AC-Link Variable Sample Rate Operation

The AC-Link serial interconnect defines a digital data and control pipe between the Controller and

the CODEC. The AC-Link supports 12 20-bit slots at 48 KHz on SDATA_IN and SDATA_OUT. The

time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastructure

that the source of each slot’s data sets or clears to indicate the validity of the slot data within the cur-

rent audio frame. This tag infrastructure can be used to support transfers between Controller and

CODEC at any sample rate.

5.2.2.

Variable Sample Rate Signaling Protocol

AC-Link’s tag infrastructure imposes FIFO requirements on both sides of the AC-Link. For example,

in passing a 44.1 KHz stream across the AC-Link, for every 480 audio output frames that are sent

across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441

PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave

Table 5. The AC-Link input slots (transmitted from the CODEC)

Slot

Name

Description

SDATA_IN TAG

MSBs indicate which slots contain valid data

STATUS ADDR read port

MSBs echo register address; LSBs indicate which slots request data

STATUS DATA read port

16-bit command register read data

3, 4

PCM L&R ADC record

20-bit PCM data from Left and Right inputs

Modem Line 1 ADC

16-bit modem data from modem Line1 input

6-11

PCM ADC Record

20-bit PCM data - Alternative Slots for Input

GPIO Status

GPIO read port and interrupt status

STAC9752 Datasheet(PDF) 30 Page - Integrated Device Technology

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