STAC9752 datasheet(61/95 Pages) IDT

61 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.1.20.

Extended Audio Control/Status (2Ah)

Default: 0400h* (*default depends on CODEC ID)

Note: If pin 48 is held high at powerup, the SPDIF is not available and bits D15:D1 can not be written and will

read back zero.

Pin 48: To Enable SPDIF, use an external 1K

Ω -10KΩ pulldown resistor. To Disable SPDIF, use an

external 1K

Ω -10KΩ pullup resistor. Do NOT leave Pin 48 floating.

D15

D14

D13

D12

D11

D10

VCFG

RESERVED

SPCV

RESERVED

SPSA1

SPSA0

RSRVD

SPDIF

RSRVD

VRA enable

Bit(s) Reset Value

Name

Description

VCFG

Determines the SPDIF transmitter behavior when data is not being

transmitted. When asserted, this bit forces the deassertion of the SPDIF

“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit

is defined in the SPDIF Control Register (Reg 3Ah).

If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),

bit[28] “Validity” flag reflects whether or not an internal CODEC transmission

error has occurred. Specifically an internal CODEC error should result in the

“Validity” flag being set to 1.

If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does not

receive a valid sample from the AC'97 controller, (Left or Right), the S/PDIF

transmitter should set the “Validity” flag to “0” and pad the “Audio Sample

Word” with “0”s for sub-frame in question. If a valid sample (Left or Right) was

received and successfully transmitted, the “Validity” flag should be “0” for that

sub-frame.

Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.

These bits can be set via driver .inf options.

14-11

Reserved

SPCV

0 = Invalid SPDIF configuration

1 = Valid SPDIF configuration

9:6

Reserved

Bit not used, should read back 0

5:4

SPSA1:SPSA0

SPDIF slot assignment

If CID[1:0] = 00 then SPSA[1:0] resets to 01

If CID[1:0] = 01 then SPSA[1:0] resets to 10

If CID[1:0] = 10 then SPSA[1:0] resets to 10

If CID[1:0] = 11 then SPSA[1:0] resets to 11

00 = left slot 3, right slot 4

01 = left slot 7, right slot 8

10 = left slot 6, right slot 9

11 = left slot 10, right slot 11

Reserved

SPDIF

0 = Disables SPDIF (SPDIF_OUT is high Z) (note 1)

1 = Enable SPDIF

SPDIF is a control register for Reg 3Ah, this bit must be set low i.e. SPDIF

disabled in order to write to Reg 3Ah Bits D15,D13:D0.

STAC9752 Datasheet(PDF) 61 Page - Integrated Device Technology

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