STAC9752 datasheet(33/95 Pages) IDT

33 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

Figure 15. AC-Link Audio Output Frame

A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-

troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-

tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97

CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 16. Start of an Audio Output Frame

SDATA_OUT’s composite stream is sent MSB first, with all non-valid slots bit positions stuffed with 0

by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid time slot, the

AC‘97 Controller always stuffs the trailing non-valid bit positions of the 20-bit slot with 0.

As an example, consider an 8-bit sample stream that is being played out to one of the STAC9752/

9753 DACs. The first 8 bit-positions are presented to the DAC (MSB first) followed by the next 12

bit-positions which are stuffed with 0 by the AC‘97 Controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least

significant bits.

When mono audio sample streams are output from the AC‘97 Controller, it is necessary that BOTH

left and right sample stream time slots be filled with the same data.

SYNC

BIT_CLK

SDATA_OUT

slot1

slot2

End of previous audio frame

slot(12)

"0"

Data Phase

20.8 uS (48 kHZ)

Tag Phase

12.288 MHz

Time Slot "Valid" Bits

Slot 1

Slot 2

Slot 3

Slot 12

("1" = time slot contains valid PCM data)

CID1 CID0

valid

"0"

Frame

"0"

SYNC

BIT_CLK

SDATA_OUT

slot1

slot2

End of previous audio frame

valid

Frame

SYNC

asserted

first

SDATA_OUT

bit of frame

SYNC

detected by

codec

STAC9752 Datasheet(PDF) 33 Page - Integrated Device Technology

STAC9752 Datasheet(HTML) 33 Page - Integrated Device Technology

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