STAC9752 datasheet(37/95 Pages) IDT

37 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.4.1.

Slot 0: TAG

Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97

CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that

the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-

tion of power-on-reset for example, while the AC‘97 CODEC’s voltage references settle. When the

AC-Link “CODEC Ready” indicator bit is a 1, it indicates that the AC-Link and AC‘97 CODEC control

and status registers are in a fully operational state. The CODEC must assert “CODEC Ready” within

400

µs after it starts receiving valid SYNC pulses from the controller, to provide indication of connec-

tion to the link and Control/Status registers are available for access. The AC‘97 Controller and

related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set

before attempting any register writes, or attempting to enable any audio stream, to avoid undesirable

audio artifacts.

Prior to any attempts at putting an AC‘97 CODEC into operation, the AC‘97 Controller should poll the

first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone

“CODEC Ready”. Once an AC‘97 CODEC is sampled “CODEC Ready”1, then the next 12 bit posi-

tions sampled by the AC‘97 Controller indicate which of the corresponding 12 time slots are

assigned to input data streams, and whether they contain valid data.

5.4.2.

Slot 1: Status Address Port / SLOTREQ signalling bits

5.4.2.1.

Status Address Port

The status port is used to monitor status for the STAC9752/9753 functions including, but not limited

to, mixer settings and power management. AC-Link input frame slot 1’s stream echoes the control

2 had been tagged “valid” by the AC‘97 CODEC during slot 0).

The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions com-

municate the associated control register address, the next 10 bits support AC‘97’s variable sample

rate signaling protocol, and the trailing 2 bit positions are stuffed with 0 by AC‘97.

5.4.2.2.

SLOTREQ signaling bits

AC-Link input frame Slot #1, the Status Address Port, now delivers CODEC control register read

address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved

least significant bits have been defined as data request flags for output slots 3-12.

1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready. It is the responsibility

of the AC’97 Controller to probe more deeply into the AC‘97 CODEC’s register file to determine which subsections

are actually ready.

Table 9. Status Address Port Bit Assignments

Bit

Description

Comments

Reserved

Stuffed with 0

18:12

Control Register Index

Echo of register index for which data is being returned

11:2

SLOTREQ

See Next Section

1:0

Reserved

Stuffed with 0

STAC9752 Datasheet(PDF) 37 Page - Integrated Device Technology

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