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C8051F360 Datasheet(PDF) 102 Page - Silicon Laboratories

Part # C8051F360
Description  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 Datasheet(HTML) 102 Page - Silicon Laboratories

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C8051F360/1/2/3/4/5/6/7/8/9
102
Rev. 1.0
9.4.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic ‘1’. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic ‘0’, selecting the feature's default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-
sponding system function.
SFR Definition 9.5. SP: Stack Pointer
Bits 7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Page:
SFR Address:
all pages
0x81
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Definition 9.6. DPL: Data Pointer Low Byte
Bits 7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
SFR Page
SFR Address:
all pages
0x82
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Definition 9.7. DPH: Data Pointer High Byte
Bits 7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
SFR Page:
SFR Address:
all pages
0x83
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0



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