C8051F360 datasheet(103/288 Pages) SILABS

103 / 288 page

Rev. 1.0

103

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 9.8. PSW: Program Status Word

Bit 7:

CY: Carry Flag.

This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow

(subtraction). It is cleared to 0 by all other arithmetic operations.

Bit 6:

AC: Auxiliary Carry Flag

This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow

from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.

Bit 5:

F0: User Flag 0.

This is a bit-addressable, general purpose flag for use under software control.

Bits 4–3: RS1–RS0: Register Bank Select.

These bits select which register bank is used during register accesses.

Bit 2:

OV: Overflow Flag.

This bit is set to 1 under the following circumstances:

• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.

• A MUL instruction results in an overflow (result is greater than 255).

• A DIV instruction causes a divide-by-zero condition.

The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other

cases.

Bit 1:

F1: User Flag 1.

This is a bit-addressable, general purpose flag for use under software control.

Bit 0:

PARITY: Parity Flag.

This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum

is even.

SFR Page:

SFR Address:

all pages

0xD0

(bit addressable)

R/WR/WR/WR/WR/WR/WR/W

Reset Value

RS1

RS0

PARITY 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

RS1

RS0

Address

0x00–0x07

0x08–0x0F

0x10–0x17

0x18–0x1F

C8051F360 Datasheet(PDF) 103 Page - Silicon Laboratories

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