C8051F360 datasheet(107/288 Pages) SILABS

107 / 288 page

Rev. 1.0

107

C8051F360/1/2/3/4/5/6/7/8/9

10. Interrupt Handler

The C8051F36x family includes an extended interrupt system supporting a total of 16 interrupt sources

with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input

pins varies according to the specific version of the device. Each interrupt source has one or more associ-

ated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid inter-

rupt condition, the associated interrupt-pending flag is set to logic ‘1’.

If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is

set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-

termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI

instruction, which returns program execution to the next instruction that would have been executed if the

interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the

hardware and program execution continues as normal. (The interrupt-pending flag is set to logic ‘1’ regard-

less of the interrupt's enable/disable state.)

Each interrupt source can be individually enabled or disabled through the use of an associated interrupt

enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be

globally enabled by setting the EA bit (IE.7) to logic ‘1’ before the individual interrupt enables are recog-

nized. Setting the EA bit to logic ‘0’ disables all interrupt sources regardless of the individual interrupt-

enable settings. Note that interrupts which occur when the EA bit is set to logic ‘0’ will be held in a pending

state, and will not be serviced until the EA bit is set back to logic ‘1’.

Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruc-

tion that has two or more opcode bytes. Using EA (global interrupt enable) as an example:

// in 'C':

EA = 0; // clear EA bit.

EA = 0; // this is a dummy instruction with two-byte opcode.

; in assembly:

CLR EA ; clear EA bit.

CLR EA ; this is a dummy instruction with two-byte opcode.

For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction

which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruc-

tion, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt ser-

vice routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be

taken.

Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.

However, most are not cleared by the hardware and must be cleared by software before returning from the

ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)

instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after

the completion of the next instruction.

10.1. MCU Interrupt Sources and Vectors

The C8051F36x MCUs support 16 interrupt sources. Software can simulate an interrupt by setting any

interrupt-pending flag to logic ‘1’. If interrupts are enabled for the flag, an interrupt request will be gener-

ated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt

sources, associated vector addresses, priority order, and control bits are summarized in Table 10.1 on

page 108. Refer to the data sheet section associated with a particular on-chip peripheral for information

regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

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