C8051F360 datasheet(108/288 Pages) SILABS

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C8051F360/1/2/3/4/5/6/7/8/9

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Rev. 1.0

10.2. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-

ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be

preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to

configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the

interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-

ity order is used to arbitrate, given in Table 10.1.

10.3. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are

sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is

5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the

ISR. Additional clock cycles will be required if a cache miss occurs (see Section 14 for more details). If an

interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to

service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other inter-

rupt is currently being serviced or the new interrupt is of greater priority) is when the CPU is performing an

RETI instruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the CPU

is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until

the current ISR completes, including the RETI and following instruction.

Table 10.1. Interrupt Summary

Interrupt Source

Interrupt

Vector

Priority

Order

Pending Flag

Enable

Flag

Priority

Control

Reset

0x0000

Top

None

N/A N/A

Always

Enabled

Always

Highest

External Interrupt 0 (/INT0) 0x0003

IE0 (TCON.1)

EX0 (IE.0) PX0 (IP.0)

Timer 0 Overflow

0x000B

TF0 (TCON.5)

ET0 (IE.1) PT0 (IP.1)

External Interrupt 1 (/INT1) 0x0013

IE1 (TCON.3)

EX1 (IE.2) PX1 (IP.2)

Timer 1 Overflow

0x001B

TF1 (TCON.7)

ET1 (IE.3) PT1 (IP.3)

UART0

0x0023

RI0 (SCON0.0)

TI0 (SCON0.1)

ES0 (IE.4) PS0 (IP.4)

Timer 2 Overflow

0x002B

TF2H (TMR2CN.7)

TF2L (TMR2CN.6)

ET2 (IE.5) PT2 (IP.5)

SPI0

0x0033

SPIF (SPI0CN.7)

WCOL (SPI0CN.6)

MODF (SPI0CN.5)

RXOVRN (SPI0CN.4)

ESPI0

(IE.6)

PSPI0

(IP.6)

SMB0

0x003B

SI (SMB0CN.0)

ESMB0

(EIE1.0)

PSMB0

(EIP1.0)

RESERVED

0x0043

N/A

N/A N/A

N/A

ADC0 Window

Comparator

0x004B

AD0WINT

(ADC0CN.5)

EWADC0

(EIE1.2)

PWADC0

(EIP1.2)

ADC0 End of Conversion

0x0053

AD0INT (ADC0STA.5) Y

EADC0

(EIE1.3)

PADC0

(EIP1.3)

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