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C8051F360 Datasheet(PDF) 124 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 124 Page - Silicon Laboratories |
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124 / 288 page  C8051F360/1/2/3/4/5/6/7/8/9 124 Rev. 1.0 SFR Definition 11.4. MAC0AL: MAC0 A Low Byte Bits 7–0: Low Byte (bits 7–0) of MAC0 A Register. SFR Page: SFR Address: 0 0xA4 R RR RRR RR Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Definition 11.5. MAC0BH: MAC0 B High Byte Bits 7–0: High Byte (bits 15–8) of MAC0 B Register. SFR Page: SFR Address: 0 0xF2 R RR RRR RR Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Definition 11.6. MAC0BL: MAC0 B Low Byte Bits 7–0: Low Byte (bits 7–0) of MAC0 B Register. A write to this register initiates a Multiply or Multiply and Accumulate operation. Note:The contents of this register should not be changed by software during the first MAC0 pipeline stage. SFR Page: SFR Address: 0 0xF1 R RR RRR RR Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 |
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