C8051F360 datasheet(128/288 Pages) SILABS

128 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

128

Rev. 1.0

12. Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this

reset state, the following occur:

•

CIP-51 halts program execution

•

Special Function Registers (SFRs) are initialized to their defined reset values

•

External Port pins are forced to a known state

•

Interrupts and timers are disabled.

All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal

data memory are unaffected during a reset; any previously stored data is preserved. However, since the

stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.

The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-

ing and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device

exits the reset state.

On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-

nal oscillator. Refer to Section “16. Oscillators” on page 169 for information on selecting and configuring

the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock

source (Section “22.3. Watchdog Timer Mode” on page 272 details the use of the Watchdog Timer). Pro-

gram execution begins at location 0x0000.

PCA

WDT

Missing

Clock

Detector

(one-

shot)

(Software Reset)

System Reset

Reset

Funnel

Px.x

SWRSF

System

Clock

CIP-51

Microcontroller

Core

Extended Interrupt

Handler

Errant

FLASH

Operation

/RST

(wired-OR)

Power On

Reset

'0'

Comparator 0

C0RSEF

VDD

Supply

Monitor

Enable

Figure 12.1. Reset Sources

C8051F360 Datasheet(PDF) 128 Page - Silicon Laboratories

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