C8051F360 datasheet(131/288 Pages) SILABS

131 / 288 page

Rev. 1.0

131

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 12.1. VDM0CN: VDD Monitor Control

Bit 7:

VDMEN: VDD Monitor Enable.

This bit turns the VDD Monitor circuit on/off. The VDD Monitor cannot generate system resets

until it is also selected as a reset source in register RSTSRC (SFR Definition 12.2). The VDD

Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the

VDD Monitor as a reset source before it has stabilized may generate a system reset.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled.

Bit 6:

VDD STAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD Monitor threshold.

1: VDD is above the VDD Monitor threshold.

Bits 5–0: RESERVED. Read = Variable. Write = don’t care.

SFR Page:

SFR Address:

all pages

0xFF

R/W

RRR

Reset Value

VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved

Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

12.3. External Reset

The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-

ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST

pin may be necessary to avoid erroneous noise-induced resets. See Table 12.1 for complete RST pin

specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

12.4. Missing Clock Detector Reset

The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system

clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a

MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,

this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables

it. The state of the RST pin is unaffected by this reset.

12.5. Comparator0 Reset

Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).

Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on

chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-

inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into

the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying

Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by

this reset.

C8051F360 Datasheet(PDF) 131 Page - Silicon Laboratories

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