C8051F360 datasheet(133/288 Pages) SILABS

133 / 288 page

Rev. 1.0

133

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 12.2. RSTSRC: Reset Source

Note:For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),

read-modify-write instructions read and modify the source enable only. [This applies to bits:

C0RSEF, SWRSF, MCDRSF, PORSF].

Bit 7:

UNUSED. Read = 0b. Write = don’t care.

Bit 6:

FERROR: Flash Error Indicator.

0: Source of last reset was not a Flash read/write/erase error.

1: Source of last reset was a Flash read/write/erase error.

Bit 5:

C0RSEF: Comparator0 Reset Enable and Flag.

0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset

source.

1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source

(active-low).

Bit 4:

SWRSF: Software Reset Force and Flag.

0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.

1: Read: Source of last reset was a write to the SWRSF bit. Write: Forces a system reset.

Bit 3:

WDTRSF: Watchdog Timer Reset Flag.

0: Source of last reset was not a WDT timeout.

1: Source of last reset was a WDT timeout.

Bit 2:

MCDRSF: Missing Clock Detector Flag.

0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing

Clock Detector disabled.

1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock

Detector enabled; triggers a reset if a missing clock condition is detected.

Bit 1:

PORSF: Power-On Reset Force and Flag.

This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD

Monitor as a reset source. Note: writing ‘1’ to this bit before the VDD Monitor is enabled

and stabilized may cause a system reset. See register VDM0CN (SFR Definition 12.1)

0: Read: Last reset was not a power-on or VDD Monitor reset. Write: VDD Monitor is not a

reset source.

1: Read: Last reset was a power-on or VDD Monitor reset; all other reset flags

indeterminate. Write: VDD Monitor is a reset source.

Bit 0:

PINRSF: HW Pin Reset Flag.

0: Source of last reset was not RST pin.

1: Source of last reset was RST pin.

SFR Page:

SFR Address:

all pages

0xEF

R/W

Reset Value

–

FERROR C0RSEF

SWRSF WDTRSF MCDRSF

PORSF

PINRSF

Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

C8051F360 Datasheet(PDF) 133 Page - Silicon Laboratories

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