C8051F360 datasheet(169/288 Pages) SILABS

169 / 288 page

Rev. 1.0

169

C8051F360/1/2/3/4/5/6/7/8/9

16. Oscillators

The C8051F36x devices include a programmable internal high-frequency oscillator, a programmable inter-

nal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator

can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as shown in

Figure 16.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the

OSCLCN register, as shown in SFR Definition 16.3. Both internal oscillators offer a selectable post-scaling

feature. The system clock can be sourced by the external oscillator circuit, either internal oscillator, or the

on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 16.1

on page 171 and Table 16.2 on page 172.

Calibrated Internal

Oscillator

SYSCLK

OSCICL

XTAL1

XTAL2

000

001

PLL

010

AGND

AV+

OSCICN

OSC

Input

Circuit

OSCXCN

Option 1

OSCLCN

OSCLF OSCLD

100

Option 4

XTAL2

Option 2

VDD

XTAL2

Option 3

XTAL2

Low Frequency

Oscillator

OSCLD

OSCLF

CLKSEL

Figure 16.1. Oscillator Diagram

16.1. Programmable Internal High-Frequency (H-F) Oscillator

All devices include a calibrated internal high-frequency oscillator that defaults as the system clock after a

system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR

Definition 16.1. OSCICL is factory calibrated to obtain a 24.5 MHz frequency.

Electrical specifications for the precision internal oscillator are given in Table 16.1 on page 171 and

Table 16.2 on page 172. Note that the system clock may be derived from the programmed internal oscilla-

tor divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8

following a reset.

C8051F360 Datasheet(PDF) 169 Page - Silicon Laboratories

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