C8051F360 datasheet(248/288 Pages) SILABS

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C8051F360/1/2/3/4/5/6/7/8/9

248

Rev. 1.0

21.1. Timer 0 and Timer 1

Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)

and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and

Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-

ter (Section “10.4. Interrupt Register Descriptions” on page 109); Timer 1 interrupts can be enabled by set-

ting the ET1 bit in the IE register (Section 10.4). Both counter/timers operate in one of four primary modes

selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD). Each

timer can be configured independently. Each operating mode is described below.

21.1.1. Mode 0: 13-bit Counter/Timer

Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration

and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same

manner as described for Timer 0.

The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions

TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or

ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to

0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are

enabled.

The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic ‘1’, high-to-low

transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section

“17.1. Priority Crossbar Decoder” on page 185 for information on selecting and configuring external I/O

pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is

clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock

Scale bits in CKCON (see SFR Definition 21.3).

Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic ‘0’ or the input signal

/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 10.7). Setting GATE0 to ‘1’

allows the timer to be controlled by the external input signal /INT0 (see Section “10.4. Interrupt Register

Descriptions” on page 109), facilitating pulse width measurements

Note: X = Don't Care

Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial

value before the timer is enabled.

TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.

Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The

input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see

SFR Definition 10.7).

TR0

GATE0

/INT0

Counter/Timer

Disabled

Enabled

Disabled

111

Enabled

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