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C8051F360 Datasheet(PDF) 246 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 246 Page - Silicon Laboratories |
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246 / 288 page  Table 20.1. SPI Slave Timing Parameters Parameter Description Min Max Units Master Mode Timing* (See Figure 20.8 and Figure 20.9) TMCKH SCK High Time 1 x TSYSCLK — ns TMCKL SCK Low Time 1 x TSYSCLK — ns TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 — ns TMIH SCK Shift Edge to MISO Change 0 — ns Slave Mode Timing* (See Figure 20.10 and Figure 20.11) TSE NSS Falling to First SCK Edge 2 x TSYSCLK — ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK — ns TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK — ns TCKL SCK Low Time 5 x TSYSCLK — ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK — ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK — ns TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns TSLH Last SCK Edge to MISO Change (CKPHA = 1 ONLY) 6 x TSYSCLK 8 x TSYSCLK ns *Note: TSYSCLK is equal to one period of the device system clock (SYSCLK). C8051F360/1/2/3/4/5/6/7/8/9 246 Rev. 1.0 |
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