C8051F360 datasheet(262/288 Pages) SILABS

262 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

262

Rev. 1.0

SFR Definition 21.13. TMR3CN: Timer 3 Control

Bit 7:

TF3H: Timer 3 High Byte Overflow Flag.

Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode,

this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is

enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine.

TF3H is not automatically cleared by hardware and must be cleared by software.

Bit 6:

TF3L: Timer 3 Low Byte Overflow Flag.

Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is

set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L

will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automat-

ically cleared by hardware.

Bit 5:

TF3LEN: Timer 3 Low Byte Interrupt Enable.

This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 inter-

rupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows.

0: Timer 3 Low Byte interrupts disabled.

1: Timer 3 Low Byte interrupts enabled.

Bit 4:

TF3CEN: Timer 3 Low-Frequency Oscillator Capture Enable.

This bit enables/disables Timer 3 Low-Frequency Oscillator Capture Mode. If TF3CEN is set

and Timer 3 interrupts are enabled, an interrupt will be generated on a rising edge of the

low-frequency oscillator output, and the current 16-bit timer value in TMR3H:TMR3L will be

copied to TMR3RLH:TMR3RLL. See Section “16. Oscillators” on page 169 for more details.

0: Timer 3 Low-Frequency Oscillator Capture disabled.

1: Timer 3 Low-Frequency Oscillator Capture enabled.

Bit 3:

T3SPLIT: Timer 3 Split Mode Enable.

When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.

0: Timer 3 operates in 16-bit auto-reload mode.

1: Timer 3 operates as two 8-bit auto-reload timers.

Bit 2:

TR3: Timer 3 Run Control.

This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only;

TMR3L is always enabled in this mode.

0: Timer 3 disabled.

1: Timer 3 enabled.

Bit 1:

UNUSED. Read = 0b. Write = don’t care.

Bit 0:

T3XCLK: Timer 3 External Clock Select.

This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit

selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock

Select bits (T3MH and T3ML in register CKCON) may still be used to select between the

external clock and the system clock for either timer.

0: Timer 3 external clock selection is the system clock divided by 12.

1: Timer 3 external clock selection is the external clock divided by 8. Note that the external

oscillator source divided by 8 is synchronized with the system clock.

SFR Page:

SFR Address:

all pages

0x91

R/W

Reset Value

TF3H

TF3L

TF3LEN

TF3CEN T3SPLIT

TR3

–

T3XCLK 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

C8051F360 Datasheet(PDF) 262 Page - Silicon Laboratories

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