TMPR4937 datasheet(450/552 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-4

15.3 Detailed Explanation

15.3.1 Interrupt sources

The TX4937 has as interrupt sources interrupts from 18 types of on-chip peripheral circuits and 6

external interrupt signals.

Table 15.3.1 lists the interrupt sources. Signals with the lower interrupt number have the higher

priority. The priorities are explained below in item. 15.3.4

The interrupt number 5 is shared between INT[3] and ETHERC1. When ETHERC1 is used, an

interrupt is noticed from ETHERC1 to the IRC interrupt number 5 internal of a chip. The external pin

INT[3] is used when ETHERC1 is used for the purpose other than an interrupt. This is the same as for

the interrupt number 6. Refer to “3.3 Pin multiplexed” for muliplexed pins.

Table 15.3.1 Interrupt Sources and Priorities

Priority

Interrupt

Number

Interrupt Source

High

SDRAM ECC Error (Internal)

TX49 Write Timeout Error (Internal)

INT[0] (External)

INT[1] (External)

INT[2] (External)

INT[3] (External) / ETHERC1 (Internal)

INT[4] (External) / ETHERC0 (Internal)

INT[5] (External)

SIO0 (Internal)

SIO1 (Internal)

DMA0[0] (Internal)

DMA0[1] (Internal)

DMA0[2] (Internal)

DMA0[3] (Internal)

IRC (Internal)

PDMAC0 (Internal)

PCIC0 (Internal)

TMR0 (Internal)

TMR1 (Internal)

TMR2 (Internal)

(Reserved)

NDFMC (Internal)

PCIERR (Internal)

PCIPMC (Internal)

ACLC (Internal)

ACLCPME (Internal)

PCIC1INT (Internal)

DMAC1[0] (Internal)

DMAC1[1] (Internal)

DMAC1[2] (Internal)

DMAC1[3] (Internal)

Low

SPI (Internal)

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