TMPR4937 datasheet(533/552 Pages) TOSHIBA

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Chapter 23 Notes on Use of TMPR4937

23-3

23.2 Notes on External Bus Controller

•

Output delay of DATA[63:0] depends on the external bus speed set with EBCCRn.SP. For details on it,

see 21.5.4 External Bus Interface AC Characteristics.

23.3 Notes on DMA Controller

•

When burst transfer is performed during DMA transfer, the increment value setting for address is

restricted. For details, see 8.3.7 Single Address Transfer and 8.3.8 Dual Address Transfer.

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Restrictions in dual address transfer by the DMA controller

[Restriction]

Setting the DMA master control register (DMMCRn) is restricted in the dual address transfer mode.

[Violation]

When a bus error occurs on a channel contained in DMAC, “all 0” may be written repeatedly to the

address (DMSARn), that should be read, in all channels including it.

In this case, the address value (DMSARn) and count register value (DMCNTRn) are not changed,

and write is continued to the same address until CPU terminates DMA transfer (0 is set to

DMCCRn.XFACT).

This violation occurs in the following conditions.

(1) FIFO is disabled. 0 is set to either one channel or more of FIFUM[n] (n=3 to 0) in DMMCR.

(2) The channel shown above (1) is set to dual address transfer. 0 is set to SNGAD in DMCCRn (n=3

to 0).

(3) A bus error occurs during access to the destination address in the channel which satisfies both (1)

and (2). 1 is set to DESERR in DMCSRn (n=3 to 0).

(4) When (3) is satisfied, single transfer (non-burst transfer) in dual address transfer mode (see

Supplemental Remarks for details) performed in any channel causes the violation shown above.

When DMMCR.FIFUM[n]=0 is set in dual address transfer mode, single transfer (non-burst

transfer) is performed regardless of the value set to DMCCRn.XFSZ.

TMPR4937 Datasheet(PDF) 533 Page - Toshiba Semiconductor