TMPR4937 datasheet(534/552 Pages) TOSHIBA

534 / 552 page

Chapter 23 Notes on Use of TMPR4937

23-4

In the case only one channel is used, restarting DMS transfer without a reset of FIFO results in a

malfunction when the conditions (1) to (3) are satisfied.

When two channels are used in a system, the following table shows settings to cause malfunctions.

Ch. A of a bus error

Ch. B

FIFO

XFSZ

Transfer

FIFO

XFSZ

Transfer

Transfer restarted

in ch. A after a bus

error (without reset

of FIFO)

Ch. B after a bus

error

Disable

Any

value

Single

Disable

Any

value

Single

Malfunction of ch. A

Malfunction of ch. B

Disable

Any

value

Single

Enable

<4DW

Single

Malfunction of ch. A

Malfunction of ch. B

Disable

Any

value

Single

Enable

≥4DW

Burst

Malfunction of ch. A

Correct operation of

ch. B 1)

1) By this setting, Channel B performs burst transfer. When the different off-set values are set to the

source address and destination address of Channel B, or source and destination burst inhibit bits

are set, single and burst transfer modes are combined for data transfer, but a malfunction does

not occur.

<Supplemental information> Dual address transfer mode

– Single transfer:

Disable FIFO (DMMCR.FIFUM[n]=0]

or the value smaller than 4DW is set to DMCCRn.XFSZ.

– Burst transfer:

Enable FIFO (DMMCR.FIFUM[n]=1]

and 4DW or larger value is set to DMCCRn.XFSZ.

[Workarounds]

Workarounds vary depending on which type of dual address transfer is performed together with dual

address single transfer. Combination of 4 channels in DMAC0 or DMAC1 affects a workaround to be

required.(DMAC0 and DMAC1 are independent controllers.)

Single Transfer

Burst Transfer

Workaround

(1)

1 ch.

Null

(a) or (b)

(2)

1 ch.

1 to 3 ch.

(b)

(3)

2 to 4 ch.

Null

(a)

(4)

2 to 3 ch.

1 to 2 ch.

(a)

Enable FIFO for all channels that perform single transfer.

(DMMCRn.FIFUM[n]=1: n=3 to 0)

(b)

After all channels finished transfers, set 1 to RSFIF in DMMCRn, then write 0 to reset and

release reset of FIFO.

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