TMPR4937 datasheet(536/552 Pages) TOSHIBA

536 / 552 page

Chapter 23 Notes on Use of TMPR4937

23-6

23.4 Note on PCI Controller

•

Set four target spaces, that are MEM0, MEM1, MEM2 and IO contained in PCI controller, so that

address windows are not duplicated. See 10.3.5 Target Access.

•

We recommend to set 0 to G2PTOCNT. See 10.4.14 G2P Timeout Count Register.

•

When TX4937 is the PCI target, access in dual address cycle is disabled. See 10.3.3 Supported PCI Bus

Commands.

•

Notes on Register Read by PCI Controller

Read the Power Status (PS) field in the PCISTATUS register (10.4.17) by the following procedures.

(1) Normal method

After checking that P2GSTATUS.PMCS bit is set, read the PCISTATUS.PS field.

(2) Method to read at any timing

To read the PCISTATUS.PS field directly without using the method (1), read the field twice

consecutively. The same value which is read twice consecutively is applied.

•

When writing to PCI bus by PDMAC of PCIC, don’t read on-chip SRAM or register in the controller

connected to G-Bus.

•

Restrictions on use of the broken master function in the PCI controller

[Restrictions]

When the broken master function in the PCI controller is used, the master which is not broken may

be incorrectly acknowledged to be broken.

•

Don’t use the broken master function

•

To use the broken master function, use only the high level containing Master A, B, C or D.

[Overview]

When the broken master function in the PCI controller is used, the master which is not broken may

be incorrectly acknowledged as the broken master.

The broken master detection function of the on-chip PCI bus arbiter detects the PCI master, which

does not start access though it has the bus, as the broken master and removes that PCI master from the

bus arbitration sequence.

When the broken master detection function detects the broken master, it may also detect the non-

broken master and acknowledge it as a broken master.

TMPR4937 Datasheet(PDF) 536 Page - Toshiba Semiconductor