TMPR4937 datasheet(538/552 Pages) TOSHIBA

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Chapter 23 Notes on Use of TMPR4937

23-8

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Note on use of the PCI boot function

[Restriction]

Don’t perform PCI boot in default setting.

[Violation]

When performing PCI boot in the default setting, 64 Mbyte memory space that is 0x0_1C00_0000 to

0x0_1FFF_FFFF (physical address, the area a and b in the figure shown below) is assigned to the PCI

bus, and not 4 Mbyte memory space that is 0x0_1FC0_0000 to 0x0_1FFF_FFFF (physical address, the

area a).

PCI boot is performed correctly. When the memory space that is 0x0_1C00_0000 to

0x0_1FBF_FFFF (physical address, the area b) is accessed after boot, malfunction occurs due to

conflict between PCIC and the other controller such as SDRAMC which assigns this memory space.

There is no problem when the memory space that is 0x0_1C00_0000 to 0x0_1FBF_FFFF (physical

address, the area b) is not accessed after boot.

This malfunciton occurs when the memory space that is 0x0_1C00_0000 to 0x0_1FBF_FFFF

(physical address) is accessed after boot. When there is no memory space that is 0x0_1C00_0000 to

0x0_1FBF_FFFF (physical address) other than PCIC, this malfunction does not occur.

[Workaround]

To assign correct memory space, change the value of G2P Memory Space 2 Address Mask Register

(G2PPM2MASK) to the following value.

Default value

Change to

G2PM2MASK(0xD148)

0x003f_fff0

0x0003_fff0

Area a

4 MB

64 MB

0x0 1C00 0000

0x0_1FFF_FFFF

0x0_1FC0_0000

0x0 1FBF FFFF

Area b

Physical address

TMPR4937 Datasheet(PDF) 538 Page - Toshiba Semiconductor