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TMPR4938 Datasheet(PDF) 448 Page - Toshiba Semiconductor |
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TMPR4938 Datasheet(HTML) 448 Page - Toshiba Semiconductor |
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448 / 716 page  Chapter 14 AC-link Controller 14-24 Bit Mnemonic Field Name Description Read/Write REGACCRDY: ACREGACC Ready R/W1C 4 REGACCRDY ACREGACC Ready R W1C 1: Indicates that the ACREGACC register is ready to get the value (in case the previous operation was a read access) and to initiate another R/W access to an AC’97 register. The result of reading or writing to the ACREGACC register before the completion notification is undefined. This bit is cleared if “1” is written to it. This bit automatically becomes ‘0’ when the ACREGACC register is written. 3:2 ⎯ Reserved ⎯ CODEC1RDY: CODEC1 Ready R 1 CODEC1RDY CODEC1 Ready R 1: Indicates that the CODEC Ready bit of SDIN1 Slot0 is set. CODEC0RDY: CODEC0 Ready R 0 CODEC0RDY CODEC0 Ready R 1: Indicates that the CODEC Ready bit of SDIN0 Slot0 is set. Figure 14.4.4 ACINTSTS Register (2/2) |
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